model sim problem

Discussion in 'VHDL' started by The Weiss Family, Jul 10, 2004.

  1. All,

    I can simulate my design just fine if I simulate the behavioral model.
    When I try to simulate anything else (mapped, placed and routed, etc...),
    I get an error saying that a generic is not part of the entity.
    It obviously is, though, because it compiles and synthesizes just fine.
    Any ideas?

    Thanks,

    Adam
     
    The Weiss Family, Jul 10, 2004
    #1
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