modeling a simple cpu

A

Ara.T.Howard

i need to model the on board cpu of a satellite in order to mock running
uploaded commands. basically i need to model the internal state and all
incoming commands so i can determine register states at a given point in time.
has anyone out there done something similar? and helpful libs? basically
i'll need something like

dmsp_cpu = cpu{
register 'oax'
register 'oal'

mem 0x55, :value => 0x2a39

instruction 'oaxload' do |value|
oax[ value ]
end
}

etc.

regards.

-a
 
D

Daniel Berger

Ara.T.Howard said:
i need to model the on board cpu of a satellite in order to mock running
uploaded commands. basically i need to model the internal state and all
incoming commands so i can determine register states at a given point in time.
has anyone out there done something similar? and helpful libs? basically
i'll need something like

dmsp_cpu = cpu{
register 'oax'
register 'oal'

mem 0x55, :value => 0x2a39

instruction 'oaxload' do |value|
oax[ value ]
end
}

What platform? What's the type of cpu? I *think* Solaris/Sparc comes
with something that will let you do this.

Regards,

Dan
 
P

Phil Tomson

i need to model the on board cpu of a satellite in order to mock running
uploaded commands. basically i need to model the internal state and all
incoming commands so i can determine register states at a given point in time.
has anyone out there done something similar? and helpful libs? basically
i'll need something like

dmsp_cpu = cpu{
register 'oax'
register 'oal'

mem 0x55, :value => 0x2a39

instruction 'oaxload' do |value|
oax[ value ]
end
}

etc.

You might want take a look at RHDL ( http://rhdl.rubyforge.org )

Phil
 
P

Phil Tomson

i was just looking at it... would you say it's a sledgehammer for this tack?

Possibly. Depends on how much modelling you need to do. RHDL has
signals which can be bit vectors (registers) and it lets you do
dataflow modelling. But yeah, maybe it's overkill for what you're
doing.

Phil
 

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