modeling connecting Processor with memory

Discussion in 'VHDL' started by Pasacco, Jun 18, 2005.

  1. Pasacco

    Pasacco Guest

    dear

    I implemented simple processor (actually simple FSM) -
    - Input port: clock, reset, data_in
    - Output prot: enable(memory enable), rw(read/write), address, data_out

    And consider Memory (Xilinx BRAM) -
    - Input port: EN, CLK, DI, RESET, WE, ADDR
    - Output port: DO

    Then I directly connected the processor with Memory, as follows.
    - processor to Memory : enable => EN, rw => we, address => ADDR,
    data_out => DI,
    - memory to processor : DO => data_in
    - clock and reset are all the same

    Problem is that

    Processor is working fine when the FSM (processor) is written as the
    following.

    ---------------------------
    architecture
    begin
    process(reset,clock)
    begin
    if reset='1' then
    CS<=Init; -- current state
    elsif clock'event and clock='1' then -- rising edge
    NS<=CS; -- next state
    end if;
    end process;

    process(ES,en,ab,Ra,Rb,cntA,cntB)
    begin
    case ES is
    when Init =>
    if a='0' then NS <= READ_MEM1;
    end if;
    when READ_MEM1 =>
    if b='1' then NS <= READ_MEM2;
    end if;
    .....
    end case;
    end process;
    Pasacco, Jun 18, 2005
    #1
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