YK said:
Hi
Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.
Yes, to model a pullup on signal 'xyz', you simply add the statement 'xyz <=
'H'' to your simulation model.
If I model using a pullup map as below:
test_ipd <= pullupmap(TO_X01Z(test))
Unfortunately this is modelling something else. What you've done is created
two signals 'test' and 'test_ipd' and created a model to separate them. But
that's not the way a pullup works. A pullup does not create a new signal,
it adds a new driver to an existing signal.
constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');
I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".
Below is a template for how you would go about modelling all of this.
entity testbench is
end testbench;
architecture RTL of testbench
signal Some_Input, Some_Output: std_logic
begin
------------------------------------------
-- DUT is the design you're trying to test
-- It has a single input and a single output
------------------------------------------
DUT : entity work.My_Design port map(
gazinta => Some_Input,
gazouta => Some_Output);
------------------------------------------
-- Lets put a pullup on 'Some_Input' and just for grins
-- put a pulldown on 'Some_Output'
------------------------------------------
Some_Input <= 'H';
Some_Output <= 'L';
------------------------------------------
-- Now lets create some arbitrary input stimulus
-- to model whatever it is that the input signal is supposed to do
------------------------------------------
process
begin
for i in 1 to 10 loop
Some_Input <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Some_Input <= 'Z';
wait; -- Wait forever
end process;
What you'll see on 'Some_Input' is that it toggles about between '1' and '0'
for 50 ns and then goes to 'H' because 'Some_Input' has two drivers; the
line "Some_Input <= 'H';" and the process above. The 'process' ends by
trying to drive the net to 'Z', the resolve function of the VHDL model for
std_logic takes the 'H' and 'Z' and resolves that to be 'H'. Similar things
would be going on with the output (whatever it does) and the 'L'.
If you stand back and take the high level look at the structure of this
testbench you would see your FPGA/CPLD (the 'My_Design' entity), a pullup
and pulldown resistor attached to some signals and then a process that
models whatever the input to 'My_Design' is....you're in fact modelling the
PCBA so you stick the pullup/down as drivers on the signals that model the
nets in your PCBA.
KJ