modelling a FIFO in VHDL

Discussion in 'VHDL' started by fpgawizz, Mar 9, 2005.

  1. fpgawizz

    fpgawizz Guest

    I am trying to send data via RS 232 to a spartan 3 development board that
    has external SRAM. I want to send data to the RXD input of the FPGA and
    have the FPGA send this to the SRAM. This is a simplex transmission from
    my PC to the FPGA that is listening. Is there any models I can see or use
    maybe for doing this kind of a UART, FIFO in VHDL ?
    fpgawizz, Mar 9, 2005
    #1
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  2. fpgawizz

    Jezwold Guest

    I assume that you have heard of the google search engine,well I suggest
    you give that a try because i did and it worked for me.
    Jezwold, Mar 10, 2005
    #2
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  3. fpgawizz

    strada

    Joined:
    Dec 21, 2008
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    Would you please not spam forums with advice that is obvious. If they tried google and it brought them here, then your comment is not very useful. the point of a forum is to offer help, not criticism
    strada, Dec 21, 2008
    #3
  4. fpgawizz

    jeppe

    Joined:
    Mar 10, 2008
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    Location:
    Denmark
    jeppe, Dec 21, 2008
    #4
  5. fpgawizz

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    this may help you..
    vhdlguru.blogspot.com/2010/03/basic-model-of-fifo-queue-in-vhdl.html
    vipinlal, Mar 10, 2010
    #5
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