Modelsim 5.7c behaviour

Discussion in 'VHDL' started by Ingmar Seifert, Oct 8, 2003.

  1. Hallo,

    I use Modelsim 5.7c since yesterday. Before this I uses 5.6e.
    I now get a warning when compiling a vhdl-file, in the following form:

    WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
    Warning: Signal "state" appears in process "steuerung"'s senstivity
    list, but it is not used in the clock expression or reset expression.

    I have set all signals, thta are read in a process in it's sensitivity
    list. Former versions of modelsim showed an error, when the signal names
    were missing. This version schows an error, when the signals are there.

    What's wrong with my code or modelsim?


    My code:
    steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy, state,CLK,RESET)
    BEGIN
    IF RESET = '1' THEN
    state <= IDLE;
    div_xs_en <= '0';
    xs_s <= (others=>'0');
    ELSIF CLK'EVENT AND CLK='1' THEN
    CASE state IS
    -- IDLE = Startzustand nach RESET
    WHEN IDLE =>
    IF HU_UNIT_EN = '1' THEN
    state <= XS;
    END IF;
    div_xs_en <= '0';

    Thanks for your help in advance.
    Regards,
    Ingmar Seifert
     
    Ingmar Seifert, Oct 8, 2003
    #1
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  2. Ingmar Seifert

    Jim Wu Guest


    > WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
    > Warning: Signal "state" appears in process "steuerung"'s senstivity
    > list, but it is not used in the clock expression or reset expression.
    >


    > steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy,

    state,CLK,RESET)

    In a clocked process, only CLK and RESET need to be in the sensitivity list.

    Jim Wu
    (remove capital letters)
    http://www.geocities.com/jimwu88/chips
     
    Jim Wu, Oct 8, 2003
    #2
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  3. On Wed, 08 Oct 2003 10:50:04 +0200, Ingmar Seifert
    <-chemnitz.de> wrote:

    >Hallo,
    >
    >I use Modelsim 5.7c since yesterday. Before this I uses 5.6e.
    >I now get a warning when compiling a vhdl-file, in the following form:
    >
    >WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
    >Warning: Signal "state" appears in process "steuerung"'s senstivity
    >list, but it is not used in the clock expression or reset expression.
    >
    >I have set all signals, thta are read in a process in it's sensitivity
    >list. Former versions of modelsim showed an error, when the signal names
    >were missing. This version schows an error, when the signals are there.
    >
    >What's wrong with my code or modelsim?



    The prevision version of Modelsim (5.6e) was wrong. The new version
    (5.7c) is correct.
    Previously, Modelsim would check that every signal used in the process
    was in the sensitivity list. This is fine for combinatorial but wrong
    for clocked processes.

    Now, it can identify clocked processes (or clocked processes with
    async resets), and checks that only the clocks and resets are in the
    sensitivity list.

    >My code:
    >steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy, state,CLK,RESET)


    should be:

    >steuerung: PROCESS(CLK,RESET)


    Regards,
    Allan.
     
    Allan Herriman, Oct 8, 2003
    #3
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