ModelSim and GHDL not producing the same output

Discussion in 'VHDL' started by blomkaal, Feb 13, 2011.

  1. blomkaal

    blomkaal

    Joined:
    Feb 13, 2011
    Messages:
    2
    Hi,

    I've written a small 1bit comparator in VHDL, but the output produced when compiled by GHDL is incorrect.

    Code:
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity eq1 is
      port (
        i0, i1 : in std_logic;
        eq : out std_logic
      );
    end eq1;
    
    architecture sop_arch of eq1 is
      signal p0, p1 : std_logic;
    begin
      -- sum of two products
      eq <= p0 or p1;
      -- product terms
      p0 <= (not i0) and (not i1);
      p1 <= i0 and i1;
    end sop_arch;
    and the testbench I'm running:
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity eq1_tb is
    end entity;
    
    architecture tb_arch of eq1_tb is
    	signal test_in0, test_in1, test_out : std_logic;
    begin
    	uut : entity work.eq1(sop_arch)
    		port map (i0 => test_in0, i1 => test_in1, eq => test_out);
    	process
    	begin
    		test_in0 <= '0';
    		test_in1 <= '0';
    		wait for 20 ns;
    		test_in0 <= '1';
    		test_in1 <= '0';
    		wait for 20 ns;
    		test_in0 <= '0';
    		test_in1 <= '1';
    		wait for 20 ns;
    		test_in0 <= '1';
    		test_in1 <= '1';
    		wait for 20 ns;
    	end process;
    end architecture;
    The output produced from inputs 1 and 1, which should be 1, is 0. I've tested the design in ModelSim, which produces the correct results.
    Am I missing something, or is there something wrong with GHDL?

    I'm running GHDL/GTKWave using the guide at
    mbmn.net/uer/tutorials/vhdl-with-ghdl/
    blomkaal, Feb 13, 2011
    #1
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  2. blomkaal

    vcraft

    Joined:
    Feb 14, 2011
    Messages:
    7
    The code looks OK.

    Perhaps you do something wrong when operating one of the simulation tools.

    E.g. you run the simulation with top level set to the eq1 itself rather than the testbench.

    Or something like that ...
    vcraft, Feb 14, 2011
    #2
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  3. blomkaal

    blomkaal

    Joined:
    Feb 13, 2011
    Messages:
    2
    That might be the case. I'm all new to this, so I'm not quite sure what you're saying :trytofly: . Could you elaborate?
    blomkaal, Feb 14, 2011
    #3
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