Modelsim Assert

Discussion in 'VHDL' started by RishiD, Nov 16, 2006.

  1. RishiD

    RishiD Guest

    Hi,

    I am still trying to learn how to create good test benches. Is it
    possible to have modelsim to like give a warning when two of my signals
    equal each other? Basically I want to run through my simulation, but
    not go through all the wave forms to see if this error occurs. I
    believe assertions are the way to go, but have never used them before.
    Anyone point me to a tutorial of some sorts?

    Thanks,

    RishiD
     
    RishiD, Nov 16, 2006
    #1
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  2. RishiD

    Guest

    The assert statement is much preferred over manually checking timing
    diagrams. That's what they're there for.

    You're looking for something like this:

    assert Signal_1 = Signal_2
    report "Signal_1 equals Signal_2"
    severity warning;

    Or better yet, try this link:
    <http://www.google.com/search?hl=en&q=vhdl+assert&btnG=Google+Search>
     
    , Nov 16, 2006
    #2
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  3. RishiD

    RishiD Guest

    Ah thanks, kept searching "Modelsim assert". Thinking it was a
    modelsim thing.

    Thanks for the help.


    wrote:
    > The assert statement is much preferred over manually checking timing
    > diagrams. That's what they're there for.
    >
    > You're looking for something like this:
    >
    > assert Signal_1 = Signal_2
    > report "Signal_1 equals Signal_2"
    > severity warning;
    >
    > Or better yet, try this link:
    > <http://www.google.com/search?hl=en&q=vhdl+assert&btnG=Google+Search>
     
    RishiD, Nov 17, 2006
    #3
  4. RishiD

    KJ Guest

    <> wrote in message
    news:...
    > The assert statement is much preferred over manually checking timing
    > diagrams. That's what they're there for.
    >
    > You're looking for something like this:
    >
    > assert Signal_1 = Signal_2
    > report "Signal_1 equals Signal_2"
    > severity warning;
    >


    Minor problem. The original post asked "Is it possible to have modelsim to
    like give a warning when two of my signals
    equal each other" which means that what needs to be asserted is that the two
    signals are NOT equal to each other so that the warning pops up when the two
    signals ARE equal to each other.

    assert Signal_1 /= Signal_2 -- or assert not(Signal_1 = Signal_2),
    whichever floats your boat
    report "Signal_1 equals Signal_2"
    severity warning; -- typically I would use 'error' here instead
    of 'warning' since it probably is a design error that needs fixing

    When using an assert you specify the condition that is supposed to be true
    so that when/if that condition is found to not be true the warning is
    printed.

    KJ
     
    KJ, Nov 17, 2006
    #4
  5. RishiD

    Ajeetha Guest

    Hi Rishi,
    As others have pointed out, VHDL's assert will do this easily. But
    there's lot more you can do with a specialized assertion language such
    as PSL (with VHDL flavor) or SVA. I wrote a PSL tutorial some time
    back, see: www.project-veripage.com

    HTH
    Ajeetha, CVC
    www.noveldv.com

    RishiD wrote:
    > Hi,
    >
    > I am still trying to learn how to create good test benches. Is it
    > possible to have modelsim to like give a warning when two of my signals
    > equal each other? Basically I want to run through my simulation, but
    > not go through all the wave forms to see if this error occurs. I
    > believe assertions are the way to go, but have never used them before.
    > Anyone point me to a tutorial of some sorts?
    >
    > Thanks,
    >
    > RishiD
     
    Ajeetha, Nov 17, 2006
    #5
  6. RishiD

    Guest

    "I left that as an exercise for the student."

    "I code them upside down on purpose to test the bench."

    Seriously, thanks for the correction.

    GH
     
    , Nov 17, 2006
    #6
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