Modelsim Delta Races

Discussion in 'VHDL' started by Andrew Greensted, Mar 15, 2006.

  1. Hi All,

    I'm hit a bit of a brick wall with a simulation problem I'm encountering.

    When simulating my (VHDL) design, Modelsim's Wave window is showing a
    'zero-width' (you can't zoom in on it) glitch on one of the signals.

    If I study the List window I can see that the signal (pcwen) does indeed
    toggle but during a delta cycle.

    ps boardclk regfede_opa portaadd
    delta regexwb_opa portawen
    cu_regfilewen pcwen
    cu_regfiledinselect

    6250000 +1 1 0000010 0000010 1 0 0000010 1 0
    6250000 +3 1 0000010 0100000 1 0 0000010 1 0
    6250000 +4 1 0000010 0100000 0 1 0000010 0 0
    6250000 +5 1 0000010 0100000 0 1 0100000 0 0
    6500000 +1 0 0000010 0100000 0 1 0100000 0 0
    6750000 +1 1 0000010 0100000 0 1 0100000 0 0
    6750000 +4 1 0000010 0100000 1 0 0100000 1 0
    6750000 +5 1 0000010 0100000 1 0 0000010 1 1 <---
    6750000 +6 1 0000010 0100000 1 0 0000010 1 0
    7000000 +1 0 0000010 0100000 1 0 0000010 1 0
    7250000 +1 1 0000010 0100000 1 0 0000010 1 0
    7250000 +3 1 0000010 0000000 1 0 0000010 1 0
    7250000 +4 1 0000010 0000000 0 1 0000010 0 0

    I'm guessing that this is due a race condition whilst the simulator
    resolves the final signal values after the clock pulse. My design is
    synchronous.

    My question is, does this suggest badly written VHDL, or is this
    something that happens with this type of simulator?

    Many Thanks
    Andy
    Andrew Greensted, Mar 15, 2006
    #1
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  2. Andrew Greensted

    Ben Jones Guest

    "Andrew Greensted" <> wrote in message
    news:dv9c9s$m2$...
    > I'm hit a bit of a brick wall with a simulation problem I'm encountering.
    > When simulating my (VHDL) design, Modelsim's Wave window is showing a
    > 'zero-width' (you can't zoom in on it) glitch on one of the signals.


    Is that actually a problem? I mean, how much did it hurt when you hit this
    wall? :)

    > If I study the List window I can see that the signal (pcwen) does indeed
    > toggle but during a delta cycle.


    > I'm guessing that this is due a race condition whilst the simulator
    > resolves the final signal values after the clock pulse. My design is
    > synchronous.
    > My question is, does this suggest badly written VHDL, or is this
    > something that happens with this type of simulator?


    No, this happens all the time. It just suggests that your "pcwen" signal is
    combinatorial (i.e. it's not the output of a register or other synchronous
    element).

    Modelsim puts it there to tell you that in real life, you might get a glitch
    under these circumstances (depending on exactly how your logic is
    implemented and what the relative timings are). Only you, the designer, can
    tell whether this would cause problems or not. (Hint: if you're using pcwen
    as the clock input to a RAM or a register, you probably have a problem.
    Otherwise, chances are you don't.)

    Cheers,

    -Ben-
    Ben Jones, Mar 15, 2006
    #2
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  3. Andrew Greensted

    Andy Guest

    >>I'm hit a bit of a brick wall with a simulation problem I'm encountering.

    > Is that actually a problem? I mean, how much did it hurt when you hit this
    > wall? :)


    Not physically, just mentally!!

    >>My question is, does this suggest badly written VHDL, or is this
    >>something that happens with this type of simulator?


    > No, this happens all the time. It just suggests that your "pcwen" signal is
    > combinatorial (i.e. it's not the output of a register or other synchronous
    > element).


    Yep, it is a combinatorial signal.

    I guess I'll just have to live with it. The glitch just stands out, and
    looks like a problem. It would be nice if the wave window, like the list
    window, had an option to only show signal values after the delta cycles
    have complete.

    Ben, your response encourages me, but I might still have a bit of a look
    to see if there's someway to avoid the glitch. But, perhaps I'm just
    being over cautious....

    Cheers
    Andy
    Andy, Mar 15, 2006
    #3
  4. Andy a écrit :

    > I guess I'll just have to live with it. The glitch just stands out, and
    > looks like a problem. It would be nice if the wave window, like the list
    > window, had an option to only show signal values after the delta cycles
    > have complete.
    >
    > Ben, your response encourages me, but I might still have a bit of a look
    > to see if there's someway to avoid the glitch. But, perhaps I'm just
    > being over cautious....



    I am afraid you can't do much about this glitch. If you combine two FF
    outputs you will have a glitch because your (real world) outputs can not
    toggle exactly at the same time. However, in synchronous design this is
    not a problem because the glitch will have disapppeared before the next
    clock edge.

    Nicolas
    (completely absurd e-mail address, do not reply directly)
    Nicolas Matringe, Mar 15, 2006
    #4
  5. Andy schrieb:
    > Yep, it is a combinatorial signal.
    >
    > I guess I'll just have to live with it. The glitch just stands out, and
    > looks like a problem. It would be nice if the wave window, like the list
    > window, had an option to only show signal values after the delta cycles
    > have complete.


    Maybe you could save such glitches by using the after clause.
    Such glitches are often harmless but may sometimes result in a mismatch
    between simulation and synthesis, so you its ever worth to have a
    detailed look on such problems.

    bye Thomas
    Thomas Stanka, Mar 16, 2006
    #5
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