Modelsim - forcing signals to 'Z'

Discussion in 'VHDL' started by DonQ, Feb 27, 2004.

  1. DonQ

    DonQ Guest

    Hi,

    I've got a simple problem with Modelsim.
    The relevant connections of my system look like that:


    ------------ ------------
    | | | |
    | | | |
    | A-----+----B |
    | | | | |
    | Module1 | | | Module2 |
    | | | | |
    ------------ | ------------
    |
    input to Module3


    A and B are declared as inout in Module1 and Module2 (it's a GPIO
    pin).

    Both Module1 and Module2 can drive the pin.
    I can't change the code of Module2 and I can't tell it to stop driving
    the pin (it drives it to '0').
    But I want the pin to be driven only by Module1, so Module3 can see
    the value driven by Module1.

    What I tried is forcing (-freeze) signal B to 'Z', but it seems not to
    work.
    Any ideas why?
    Can I do something else?

    Thanks,
    DonQ
     
    DonQ, Feb 27, 2004
    #1
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  2. DonQ

    Chuck Gales Guest

    On Fri, 27 Feb 2004 12:45:30 -0800, DonQ wrote:

    > Hi,
    >
    > I've got a simple problem with Modelsim. The relevant connections of my
    > system look like that:
    >
    >
    > ------------ ------------
    > | | | |
    > | | | |
    > | A-----+----B |
    > | | | | |
    > | Module1 | | | Module2 |
    > | | | | |
    > ------------ | ------------
    > |
    > input to Module3
    >
    >
    > A and B are declared as inout in Module1 and Module2 (it's a GPIO pin).
    >
    > Both Module1 and Module2 can drive the pin. I can't change the code of
    > Module2 and I can't tell it to stop driving the pin (it drives it to '0').
    > But I want the pin to be driven only by Module1, so Module3 can see the
    > value driven by Module1.
    >
    > What I tried is forcing (-freeze) signal B to 'Z', but it seems not to
    > work.
    > Any ideas why?
    > Can I do something else?
    >
    > Thanks,
    > DonQ

    Why don't you OR the signals from Module1 and Module2 to the input of
    Module3?? If Module2 is always 0, then Module3 will see only the value of
    the signal from Module1??

    Chuck
     
    Chuck Gales, Feb 28, 2004
    #2
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  3. DonQ wrote:
    > Hi,
    >
    > I've got a simple problem with Modelsim.
    > The relevant connections of my system look like that:
    >
    >
    > ------------ ------------
    > | | | |
    > | | | |
    > | A-----+----B |
    > | | | | |
    > | Module1 | | | Module2 |
    > | | | | |
    > ------------ | ------------
    > |
    > input to Module3
    >
    >
    > A and B are declared as inout in Module1 and Module2 (it's a GPIO
    > pin).
    >
    > Both Module1 and Module2 can drive the pin.
    > I can't change the code of Module2 and I can't tell it to stop driving
    > the pin (it drives it to '0').
    > But I want the pin to be driven only by Module1, so Module3 can see
    > the value driven by Module1.
    >
    > What I tried is forcing (-freeze) signal B to 'Z', but it seems not to
    > work.
    > Any ideas why?
    > Can I do something else?
    >
    > Thanks,
    > DonQ


    This is your JOB to fix A or B to 'Z, not Modelsim JOB.
    But your modules need to know when there are output or tristate. You
    have to do a control with an 'output enable' or other control
    signal(chip select + read signal), like

    -- example: A and B are 8-bit vector
    A <= "00110011" WHEN (A_OE = '1') ELSE (OTHERS => 'Z');
    B <= "11001100" WHEN (B_OE = '1') ELSE (OTHERS => 'Z');
    -- works if B_OE <= not(A_OE);

    Just try.

    Laurent
    www.amontec.com
     
    Amontec Team, Laurent Gauch, Feb 28, 2004
    #3
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