MODELSIM : library generation and mapping

Discussion in 'VHDL' started by Pasacco, May 24, 2007.

  1. Pasacco

    Pasacco Guest

    Hi

    Hopefully I am allowed ask (kind of) MODELSIM tool problem :)

    I have problem when I try to do COMPILE bunch of VHDL source files.

    VHDL source files have hierarchical structure.

    --------------------------------------------------------------------------------------------
    --- For example, VHDL code looks like below
    ---
    --- Name of LIBRARY of "module_network" : module_networklib
    --- module_network_pkg : definition of component "module_network
    ---
    LIBRARY module_networklib;
    USE module_networklib.module_network_pkg.ALL;
    --------------------------------------------------------------------------------------------

    Problem is that

    When I try to compile the module (in MODELSIM), the tool responds with
    error message
    Error:(vom-19) Failed to access library 'module_networklib' at
    "module_networklib"

    This is obviously expected, since I do not have "compiled library".

    I thought that MODELSIM automatically compiles and creates library.

    How can we create "compiled library" for sub-modules ?

    Thank you in advance for someone, who has this experience.
     
    Pasacco, May 24, 2007
    #1
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  2. Pasacco

    Paul Floyd Guest

    On 24 May 2007 11:09:18 -0700, Pasacco <> wrote:
    > Hi
    >
    > Hopefully I am allowed ask (kind of) MODELSIM tool problem :)
    >
    > I have problem when I try to do COMPILE bunch of VHDL source files.
    >
    > VHDL source files have hierarchical structure.
    >
    > --------------------------------------------------------------------------------------------
    > --- For example, VHDL code looks like below
    > ---
    > --- Name of LIBRARY of "module_network" : module_networklib
    > --- module_network_pkg : definition of component "module_network
    > ---
    > LIBRARY module_networklib;
    > USE module_networklib.module_network_pkg.ALL;
    > --------------------------------------------------------------------------------------------
    >
    > Problem is that
    >
    > When I try to compile the module (in MODELSIM), the tool responds with
    > error message
    > Error:(vom-19) Failed to access library 'module_networklib' at
    > "module_networklib"
    >
    > This is obviously expected, since I do not have "compiled library".
    >
    > I thought that MODELSIM automatically compiles and creates library.
    >
    > How can we create "compiled library" for sub-modules ?
    >
    > Thank you in advance for someone, who has this experience.


    Hi

    You should do something like

    vlib module_networklib
    vcom module_networklib.vdl

    A bientot
    Paul
    (Not speaking for Mentor Graphics)
     
    Paul Floyd, May 24, 2007
    #2
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  3. Pasacco

    Pasacco Guest

    > vlib module_networklib
    > vcom module_networklib.vdl


    Library directory is generated and I can see in the MODELSIM GUI.
    'vlib' seems okay.

    'vcom' is still problematic.

    When I type,

    Library directory > vcom "VHDL file"

    Strangely, following error is encountered.

    ----------------------------------------
    ** Error: (vcom-19) Failed to access library 'work' at "work".
    No such file or directory. (errno = ENOENT)
    ----------------------------------------

    My intention was NOT to use 'work' library.
    If anyone has idea, please let me know.
     
    Pasacco, May 24, 2007
    #3
  4. Paul Floyd wrote:

    > You should do something like
    >
    > vlib module_networklib
    > vcom module_networklib.vdl


    Don't forget the -work option to actually compile into library
    module_networklib:

    vcom -work module_networklib module_networklib.vdl

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, May 24, 2007
    #4
  5. Pasacco

    Duane Clark Guest

    Pasacco wrote:
    > Hi
    >
    > Hopefully I am allowed ask (kind of) MODELSIM tool problem :)
    >
    > I have problem when I try to do COMPILE bunch of VHDL source files.
    >
    > VHDL source files have hierarchical structure.
    >
    > --------------------------------------------------------------------------------------------
    > --- For example, VHDL code looks like below
    > ---
    > --- Name of LIBRARY of "module_network" : module_networklib
    > --- module_network_pkg : definition of component "module_network
    > ---
    > LIBRARY module_networklib;
    > USE module_networklib.module_network_pkg.ALL;
    > --------------------------------------------------------------------------------------------


    First off, do you really need a library? Is this code all in the same
    directory, or is the module_networklib in another directory somewhere
    and will be used in other projects? If all this code is in the same
    directory and will only be used in this project, then you probably don't
    want a library; just compile everything into work.

    Assuming you are sure you want a library, and that the code for
    module_networklib is in another directory... I would normally simply
    create a work directory there named "work" and compile the source into
    it normally. Then in the project file where you want to use the library
    (modelsim.ini or project.mpf), in the [Library] section add a library
    mapping:
    module_networklib = /path_to_library/work
     
    Duane Clark, May 24, 2007
    #5
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