Modelsim loading problem

Discussion in 'VHDL' started by AG, Mar 7, 2006.

  1. AG

    AG Guest

    Hi,

    I am trying to simulate a design, Modelsim don't want to load it.

    Compilation is successful.

    When I load my top-level entity (a test bench), Modelsim I get the following
    message :

    # Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
    # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
    # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
    # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body)
    # Loading work.tb_filter(test1)
    # Loading work.two_filters(simple)
    # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
    # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
    # Loading work.fir(transverse)
    # ** Failure: (vsim-3807) Types do not match between component and entity
    for port x
    # Time: 0 ns Iteration: 0 Instance: /tb_filter/uut/filtre1 File:
    C:/Dev/Test/vhdl/FIR/filter.vhd
    # Fatal error at C:/Dev/Test/vhdl/FIR/filter.vhd line 114
    # while elaborating region: /tb_filter/uut/filtre1
    # Load interrupted

    Of course I have checked the types on the component and the entity, and they
    are exactly the same signed(2*N-1 downto 0) where N is a generic set to 32.

    What I a wondering is why does modelsim load ieee.std_logic_arith(body) and
    ieee.std_logic_unsigned(body) ?
    I don't mention them in my source files (the only one I use is
    ieee.std_logic_1164.all and ieee.numeric_std.all), and I am suspecting these
    libraries to interfere with ieee.numeric_std, especially for the definition
    of the type signed.

    Am I wrong ? If not, what to do ? If yes why ?

    Thank you,

    Alexandre.
     
    AG, Mar 7, 2006
    #1
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  2. AG

    AG Guest

    I found the problem :

    Modelsim wasn't pointing at the right file. The other file was loading the
    libraries...
     
    AG, Mar 7, 2006
    #2
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