Modelsim Post-synthesis

Discussion in 'VHDL' started by DualCore, Oct 12, 2006.

  1. DualCore

    DualCore

    Joined:
    Sep 27, 2006
    Messages:
    4
    hi ,

    i am trying to simulate a post-synthesis vhdl file generated by Xilinx Webpak , does anybody know how to include and use this file in modelsim independently ???:)
    DualCore, Oct 12, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    2,071
    Ralf Hildebrandt
    Sep 8, 2003
  2. walala
    Replies:
    4
    Views:
    1,170
    Technology Consultant
    Sep 9, 2003
  3. sergey
    Replies:
    2
    Views:
    1,952
    Mike Treseler
    Nov 7, 2006
  4. fpgaengineer
    Replies:
    7
    Views:
    3,680
    Mike Treseler
    Mar 12, 2007
  5. scott.yuan523@gmail.com

    Post Synthesis, Post PAR, and real hardware behavior?

    scott.yuan523@gmail.com, Apr 25, 2007, in forum: VHDL
    Replies:
    5
    Views:
    1,132
    Thomas Stanka
    Apr 27, 2007
Loading...

Share This Page