Ajeetha said:
AFAIK it does - you may have some escaped names that may cause some
trouble - can you show what problem you face?
Ajeetha
www.noveldv.com
Thanks,
Is always the same old problem when all signals name disappear on the post
route timing simulation.
I prefer to use Altera FPGA's and Quartus because the post-fitting registers
are more legible and vectors don't split up.
Now I'm very interested by the Lattice XP family on a very complex design
with a 80MHz clock processor with double port memory, registers, pipelining
and a lot of peripherals.
Because getting maximum MIPS is crucial, each instruction is time-variable.
For example a jump will take 3 clocks, a read or write from memory 4 clocks,
and a 16-bit multiplication will need 6 clocks.
After synthesis, the estimated frequency is only 27.4MHz, because I don't
now how "to inform" the synthesizer that I'll wait 6 clock until the
multiplication is done.
This means that timing report is useless for me and I need to "see" what
happened inside the FPGA.
I hope I was clear enough.
Dan.