ModelSim - vcom dependency order

Discussion in 'VHDL' started by andyesquire@hotmail.com, Mar 8, 2005.

  1. Guest

    Hi,

    Does anybody know a way to automatically generate the correct compile
    order in ModelSim without using the GUI?

    Compiling via the GUI finds the correct compile order, but there does
    not seem to be an equivalent way to do this from the command line or in
    a TCL script - if you have 50 .vhd files, do you have to manually
    figure out all the dependencies and manually enter the vcom commands in
    the correct order? That would be very time consuming.

    What I'm looking for is something like vcom -R toplevel.vhd where -R
    means recursively compile but sadly this is lacking from the user
    manual :)

    TIA,

    Andy.
     
    , Mar 8, 2005
    #1
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  2. wrote:

    > Does anybody know a way to automatically generate the correct compile
    > order in ModelSim without using the GUI?


    If you have "make" you use
    modelsim "vmake" and say

    vmake > Makefile
    make test_my_design

    Emacs vhdl-mode has a slightly fancier
    makefile generator.

    -- Mike Treseler
     
    Mike Treseler, Mar 8, 2005
    #2
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  3. Mike Treseler wrote:

    > wrote:
    >
    >> Does anybody know a way to automatically generate the correct compile
    >> order in ModelSim without using the GUI?

    >
    > If you have "make" you use
    > modelsim "vmake" and say
    >
    > vmake > Makefile
    > make test_my_design
    >
    > Emacs vhdl-mode has a slightly fancier
    > makefile generator.


    That works great, if you already have a successfully compiled design in
    the 'work' library. If you don't . . .

    A brute force, but very simple, method is to create a batch file that
    compiles all the files, in any order, and then loops back to start over
    if there is an error in any of the compiles. Eventually, all
    dependencies will be resolved by one of the previous compile iterations
    and the loop can exit. Then you can run the vmake steps Mike outlines
    and get the correct compile order.

    You can reduce the number of iterations by grouping the compiles so that
    all packages compile before any sources. It is a truly nasty technique
    but it does work and costs nothing but computer time so fire it up and
    go to lunch.

    There are some free tools available that will extract the hierarchy for
    you, but you still end up having to translate the output into a compile
    script. This way, you should be able to write a generic script and just
    run it on each new project.

    I don't usually use this technique (I update my build script each time I
    add a new file) but it saves a lot of pain if you're taking over a
    project that doesn't have a build script.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Mar 9, 2005
    #3
  4. Klaus Falser Guest

    In article <>,
    says...
    > wrote:
    >
    > > Does anybody know a way to automatically generate the correct compile
    > > order in ModelSim without using the GUI?

    >
    > If you have "make" you use
    > modelsim "vmake" and say
    >
    > vmake > Makefile
    > make test_my_design
    >
    > Emacs vhdl-mode has a slightly fancier
    > makefile generator.
    >
    > -- Mike Treseler
    >


    Vmake is able only to extract the dependencies from a
    library. You have to compile your design at least once
    manually in the correct order for using vmake.

    If the question was about a tool which starts from a
    top level entity and collects all subentities generating
    a makefile, then vmake is of no help, but I believe
    emacs vhdl-mode does the job.

    Best regards
    Klaus
     
    Klaus Falser, Mar 9, 2005
    #4
  5. Alan Fitch Guest

    "Tim Hubberstey" <> wrote in message
    news:eek:yxXd.11964$i6.7140@edtnps90...
    > Mike Treseler wrote:
    >
    > > wrote:
    > >
    > >> Does anybody know a way to automatically generate the correct

    compile
    > >> order in ModelSim without using the GUI?

    > >
    > > If you have "make" you use
    > > modelsim "vmake" and say
    > >
    > > vmake > Makefile
    > > make test_my_design
    > >
    > > Emacs vhdl-mode has a slightly fancier
    > > makefile generator.

    >
    > That works great, if you already have a successfully compiled design

    in
    > the 'work' library. If you don't . . .
    >
    > A brute force, but very simple, method is to create a batch file

    that
    > compiles all the files, in any order, and then loops back to start

    over
    > if there is an error in any of the compiles. Eventually, all
    > dependencies will be resolved by one of the previous compile

    iterations
    > and the loop can exit. Then you can run the vmake steps Mike

    outlines
    > and get the correct compile order.
    >
    > You can reduce the number of iterations by grouping the compiles so

    that
    > all packages compile before any sources. It is a truly nasty

    technique
    > but it does work and costs nothing but computer time so fire it up

    and
    > go to lunch.
    >
    > There are some free tools available that will extract the hierarchy

    for
    > you, but you still end up having to translate the output into a

    compile
    > script. This way, you should be able to write a generic script and

    just
    > run it on each new project.
    >
    > I don't usually use this technique (I update my build script each

    time I
    > add a new file) but it saves a lot of pain if you're taking over a
    > project that doesn't have a build script.
    > --
    > Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting

    Engineer
    > Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded

    systems
    > Vancouver, BC, Canada . . . . . . . . . . .

    http://www.marmot-eng.com
    >
     
    Alan Fitch, Mar 9, 2005
    #5
  6. Alan Fitch Guest

    "Tim Hubberstey" <> wrote in message
    news:eek:yxXd.11964$i6.7140@edtnps90...
    > Mike Treseler wrote:
    >
    > > wrote:
    > >
    > >> Does anybody know a way to automatically generate the correct

    compile
    > >> order in ModelSim without using the GUI?

    > >
    > > If you have "make" you use
    > > modelsim "vmake" and say
    > >
    > > vmake > Makefile
    > > make test_my_design
    > >
    > > Emacs vhdl-mode has a slightly fancier
    > > makefile generator.

    >
    > That works great, if you already have a successfully compiled design

    in
    > the 'work' library. If you don't . . .
    >
    > A brute force, but very simple, method is to create a batch file

    that
    > compiles all the files, in any order, and then loops back to start

    over
    > if there is an error in any of the compiles. Eventually, all
    > dependencies will be resolved by one of the previous compile

    iterations
    > and the loop can exit. Then you can run the vmake steps Mike

    outlines
    > and get the correct compile order.
    >
    > You can reduce the number of iterations by grouping the compiles so

    that
    > all packages compile before any sources. It is a truly nasty

    technique
    > but it does work and costs nothing but computer time so fire it up

    and
    > go to lunch.
    >
    > There are some free tools available that will extract the hierarchy

    for
    > you, but you still end up having to translate the output into a

    compile
    > script. This way, you should be able to write a generic script and

    just
    > run it on each new project.
    >
    > I don't usually use this technique (I update my build script each

    time I
    > add a new file) but it saves a lot of pain if you're taking over a
    > project that doesn't have a build script.
    > --



    Another thing you can try to create the correctly compiled library is
    to
    compile using vcom -just, e.g. compile packages, then entities, then
    package
    bodies, then architectures, then configurations. I.e.

    vcom -just p *.vhd
    vcom -just e *.vhd
    vcom -just pb *.vhd
    vcom -just a *.vhd
    vcom -just c *.vhd

    regards

    Alan

    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

    Fax: +44 (0)1425 471573 Web:
    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Mar 9, 2005
    #6
  7. Alan Fitch wrote:

    >>Mike Treseler wrote:
    >>
    >>
    >>> wrote:
    >>>
    >>>
    >>>>Does anybody know a way to automatically generate the correct

    >
    > compile
    >
    >>>>order in ModelSim without using the GUI?
    >>>
    >>>If you have "make" you use
    >>>modelsim "vmake" and say
    >>>
    >>>vmake > Makefile
    >>>make test_my_design

    >


    > Another thing you can try to create the correctly compiled library is
    > to
    > compile using vcom -just, e.g. compile packages, then entities, then
    > package
    > bodies, then architectures, then configurations. I.e.
    >
    > vcom -just p *.vhd
    > vcom -just e *.vhd
    > vcom -just pb *.vhd
    > vcom -just a *.vhd
    > vcom -just c *.vhd


    That will certainly result in many fewer errors but I don't think it
    accounts for dependencies within configurations. If the configuration in
    a.vhd calls out b.vhd, won't you be toast?


    I decided that I should write a Windows script to do the iterative
    compile method in case I need it later. I'm releasing it under GPL and
    you can get it from:

    <http://www.geocities.com/marmoteng/brute_vcom_v0.1.zip>

    There's no documentation, for now, except what's in the source. OTOH,
    there's no options either so it shouldn't need much documentation. Just
    run it from a command window (Windows 2000 or XP) and it will
    iteratively compile all .vhd files in the directory.

    Suggestions through my homepage are welcome -- action on any suggestions
    not guaranteed. ;)
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Mar 9, 2005
    #7
  8. Guest

    Mike - Thanks that's a good solution, unfortunately I'm on Windows but
    maybe I can get make under Cygwin to work, although as Klaus pointed
    out this does require a fully compiled design.

    Tim - The brute force approach, I like it but if I have to write any
    code then I'd go all out and write a Java program but that's a few days
    of effort (call me a masochist).

    Alan - I'll try this, but does it work if there are dependencies at the
    same level in the tree that are not compiled in the order elaborated by
    the *.vhd wildcard?

    Andy.
     
    , Mar 9, 2005
    #8
  9. ALuPin Guest

    Hi,

    try the following .do file (Execute Macro)
    When opening Modelsim stand-alone you should CHANGE DIRECTORY to
    D:/project_directory/simulation/modelsim

    # Here starts the macro file
    vlib work
    cd D:/project_directory/simulation/modelsim
    set SRC_DIR "D:/project_directory"

    # Enter the correct order of files to compile
    vcom ${SRC_DIR}/vhdl_file1.vhd
    vcom ${SRC_DIR}/vhdl_file2.vhd
    ....
    vcom ${SRC_DIR}/vhdl_file100.vhd

    vcom ${SRC_DIR}/simulation/modelsim/tb_testbench.vhd

    vsim tb_testbench

    do wave.do

    run 10ms -all

    configure wave -signalnamewidth 1
    set StdArithNoWarnings 1
    set IgnoreWarning 1
    set DefaultRadix unsigned

    ----------
    Hope this helps

    Rgds
    André
     
    ALuPin, Mar 9, 2005
    #9
  10. Alan Fitch Guest

    wrote:
    > Mike - Thanks that's a good solution, unfortunately I'm on Windows but
    > maybe I can get make under Cygwin to work, although as Klaus pointed
    > out this does require a fully compiled design.
    >
    > Tim - The brute force approach, I like it but if I have to write any
    > code then I'd go all out and write a Java program but that's a few days
    > of effort (call me a masochist).
    >
    > Alan - I'll try this, but does it work if there are dependencies at the
    > same level in the tree that are not compiled in the order elaborated by
    > the *.vhd wildcard?
    >


    I don't think it does. But it "often" works :)

    regards

    Alan
    --
    Alan Fitch
    Doulos Ltd
    http://www.doulos.com
     
    Alan Fitch, Mar 9, 2005
    #10
  11. Hans Guest

    Hi Andy,

    I have a simple utility on my website to sort out dependency, this might
    help you out, see:

    http://www.ht-lab.com/freeutils/vhdlsort/vhdlsort.html

    Hans.
    www.ht-lab.com

    <> wrote in message
    news:...
    |
    | Hi,
    |
    | Does anybody know a way to automatically generate the correct compile
    | order in ModelSim without using the GUI?
    |
    | Compiling via the GUI finds the correct compile order, but there does
    | not seem to be an equivalent way to do this from the command line or in
    | a TCL script - if you have 50 .vhd files, do you have to manually
    | figure out all the dependencies and manually enter the vcom commands in
    | the correct order? That would be very time consuming.
    |
    | What I'm looking for is something like vcom -R toplevel.vhd where -R
    | means recursively compile but sadly this is lacking from the user
    | manual :)
    |
    | TIA,
    |
    | Andy.
    |
     
    Hans, Mar 9, 2005
    #11
  12. Tim Hubberstey wrote:

    > That works great, if you already have a successfully compiled design in
    > the 'work' library.


    Actually vhdl-mode make will do the compiles also.

    -- Mike Treseler
     
    Mike Treseler, Mar 9, 2005
    #12
  13. wrote:

    > Mike - Thanks that's a good solution, unfortunately I'm on Windows but
    > maybe I can get make under Cygwin to work, although as Klaus pointed
    > out this does require a fully compiled design.
    >
    > Tim - The brute force approach, I like it but if I have to write any
    > code then I'd go all out and write a Java program but that's a few days
    > of effort (call me a masochist).
    >
    > Alan - I'll try this, but does it work if there are dependencies at the
    > same level in the tree that are not compiled in the order elaborated by
    > the *.vhd wildcard?

    You can also use ghdl (http://ghdl.free.fr), which is able to automatically
    find an analysis order.

    Tristan.
     
    Tristan Gingold, Mar 12, 2005
    #13
  14. Bert Cuzeau Guest

    ALuPin wrote:
    > Hi,
    >
    > try the following .do file (Execute Macro)
    > When opening Modelsim stand-alone you should CHANGE DIRECTORY to
    > D:/project_directory/simulation/modelsim
    >
    > # Here starts the macro file
    > vlib work
    > cd D:/project_directory/simulation/modelsim


    I would remove this "cd" line,
    (If you're not there before creating work, it'll fail.)
    or I would move "vlib work" after cd

    > set SRC_DIR "D:/project_directory"
    >
    > # Enter the correct order of files to compile
    > vcom ${SRC_DIR}/vhdl_file1.vhd
    > vcom ${SRC_DIR}/vhdl_file2.vhd
    > ...
    > vcom ${SRC_DIR}/vhdl_file100.vhd
    >
    > vcom ${SRC_DIR}/simulation/modelsim/tb_testbench.vhd
    >
    > vsim tb_testbench
    >
    > do wave.do
    >
    > run 10ms -all


    ???
    either run -a
    or
    run 10ms ?

    ---
    My $0.01 addition to the numerous posts :

    Compile :
    - Packages first
    - Configurations last

    In between compilation :
    - is mostly order INdependent if you use components.
    - must be bottom-up if you use direct instanciation of entities.
    - if entities and arch are in separate files,
    then entities must compile first.

    In any case, test benches are often easy to spot if there
    is an enforced naming convention in place and you can compile
    them last (before configs) just in case.

    If the naming conventions says (for example) that packages
    end with _pk, test benches end with _tb and configs with _cf,
    since .do files are Tcl, you can use simple regular expressions
    to compile the .vhd files in the mentioned above order.
    The only remaining issue is if you use direct instanciation
    outside test benches.

    BTW : I believe emacs vhdl mode does this dependancy checking
    (not 100% sure though).

    In practice, we do NOT do this above :
    As someone else said, I don't like compiling just anything wildly
    in a project ! Having a wrong file compiled in a project can be a major
    source of frustration.
    We have Tcl scripts for each project, and we carefully select the files
    that we compile (and those we don't), and the compilation order comes
    naturally.

    A text file containing the list of design files to compile for a given
    project is a true blessing : you can use it in your simulation script,
    synthesis script (Quartus, Synplify, Leonardo, Precision...) and for
    archival script (and make if you want) too.

    Bert Cuzeau
     
    Bert Cuzeau, Apr 4, 2005
    #14
  15. Bert Cuzeau wrote:

    > In between compilation :
    > - is mostly order INdependent if you use components.
    > - must be bottom-up if you use direct instanciation of entities.


    True. The downside to components
    is keeping port changes lined up.

    > BTW : I believe emacs vhdl mode does this dependancy checking
    > (not 100% sure though).


    True for the working library.
    Other library references must be
    pre-compiled and mapped before using
    the emacs vhdl-generate-makefile command.
    You can grab an ordered file list
    with the shell commands:

    make clean
    make my_design_tb

    -- Mike Treseler
     
    Mike Treseler, Apr 4, 2005
    #15
  16. Eric DELAGE Guest

    I use ModelSim on windows. Its embedded TCL interpreter has some
    commands for you. You should type 'help project' in the interpreter to
    see how it works.

    There are things like project add <your_file>, project compileall, ...
    The only limitation that I have found is that I still don't have
    understand how I can associate such or such VHDL file to such or such
    symbolic library name. Any idea?

    Eric

    wrote:
    > Hi,
    >
    > Does anybody know a way to automatically generate the correct compile
    > order in ModelSim without using the GUI?
    >
    > Compiling via the GUI finds the correct compile order, but there does
    > not seem to be an equivalent way to do this from the command line or in
    > a TCL script - if you have 50 .vhd files, do you have to manually
    > figure out all the dependencies and manually enter the vcom commands in
    > the correct order? That would be very time consuming.
    >
    > What I'm looking for is something like vcom -R toplevel.vhd where -R
    > means recursively compile but sadly this is lacking from the user
    > manual :)
    >
    > TIA,
    >
    > Andy.
    >
     
    Eric DELAGE, Apr 5, 2005
    #16
  17. Eric DELAGE wrote:
    > I use ModelSim on windows. Its embedded TCL interpreter has some
    > commands for you. You should type 'help project' in the interpreter to
    > see how it works.
    > There are things like project add <your_file>, project compileall, ...
    > The only limitation that I have found is that I still don't have
    > understand how I can associate such or such VHDL file to such or such
    > symbolic library name.


    try typing "vmap" from your source directory.
    This will show you what is already available to USE.

    Let's see what I get:

    228 steptoe > vmap
    Reading modelsim.ini
    "work" maps to directory mylibdir.
    "mylib" maps to directory mylibdir.
    Reading /steptoe/usr1/modeltech/linux/../modelsim.ini
    "std" maps to directory /steptoe/usr1/modeltech/linux/../std.
    "ieee" maps to directory /steptoe/usr1/modeltech/linux/../ieee.
    "verilog" maps to directory /steptoe/usr1/modeltech/linux/../verilog.
    "vital2000" maps to directory /steptoe/usr1/modeltech/linux/../vital2000.

    Next study and play with commands using library options:

    vlib mylibdir
    vcom -work mylibdir mycode.vhd
    vdir -lib mylibdir
    vmap mylib mylibdir
    vmap
    vmap work mylibdir
    vmap
    vcom mycode.vhd
    vsim -c mycode
    vdir

    Modelsim does a good job on its
    waveform, debug and shell windows.
    I can't say anything nice about
    the GUI project manager
    so I won't say anything at all.


    -- Mike Treseler
     
    Mike Treseler, Apr 5, 2005
    #17
  18. Mike Treseler wrote:
    > Modelsim does a good job on its waveform, debug and shell windows. I
    > can't say anything nice about the GUI project manager so I won't say
    > anything at all.


    ModelSim's project manager GUI does one thing quite well... it allows
    you to bypass it completely and do everything from the command line
    and/or scripts. I haven't used the GUI for years. :)
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Apr 6, 2005
    #18
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