ModelSim Verilog problem with simple simulation

Discussion in 'VHDL' started by bbiandov, Oct 20, 2007.

  1. bbiandov

    bbiandov

    Joined:
    Sep 24, 2006
    Messages:
    3
    Hi

    I'm trying to do the simplest of things - to run the counter.v and tcounter.v simulation and create a waveform. However once compiled, I have no objects hence nothing that can be added to the waveform. I get no errors at all, just no objects after I compile. I see the two files under my library, I can click ont he testbench file and it opens in SIM but objects window is just empty. Attempting to add to waveform casues error - no objects found?

    The funny thing is that if I compile the exact same design and testbench but use the vhdl versions, then I do have objects available to add to a waveform.

    What gives? Are the Verilog examples counter.v and tcounter.v screwed? They came from the original distribution and most of all - I get to compile them with no errors?

    Thanks
    ~B
     
    bbiandov, Oct 20, 2007
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  2. bbiandov

    scottcarl

    Joined:
    May 4, 2007
    Messages:
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    Location:
    USA
    bbiandov,

    It sounds like you don't have the Verilog license, only the VHDL. Modelsim will allow you to compile any type of code(VHDL or Verilog) but you must purchase the Verilog simulator license if you want to see the signals. I hope you've got a couple thousand spare dollars for it. Check out Aldec Active-HDL for a better mixed mode simulator than Modelsim. ($5000 for mixed language mode).

    Scott
     
    scottcarl, Oct 22, 2007
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  3. bbiandov

    bbiandov

    Joined:
    Sep 24, 2006
    Messages:
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    Found the problem - disable optimization. Then all objects show up..

    VoptFlow = 0 in modelsim.ini

    ~B
     
    Last edited: Oct 22, 2007
    bbiandov, Oct 22, 2007
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