Modelsim Warning

[FPGA]

I am getting the following warning in Modelsim

# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.

When I run simulations, I do not see any waveforms and it just freezes
there forever. My design size if around 1000 lines. I do have other
vhdl files for other projects. I have Modelsim Student edition.

How do I fix this problem?

Thanks

 

[scottcarl]

Ahhh Modelsim,

You have apparently happened upon another outstanding bug hidden within this horendous software tool (Modelsim that is). Try to get away from Modelsim as quickly as possible for many other catestrophic bugs lurk within its domain. I'm sure I'll get some heat over this comment but these bugs have existed in Modelsim for over 10 years and they don't feel the need to ever fix them.
However, it almost sounds like you are running up against a certain initialization runtime error that occurs when thousands of loops(delta times) run before actually starting the simulation. There is a switch somewhere that allows you to increase this startup/initialization loop count to a much hight number, like 100,000 possibly that will allow your simulation to start up.
Scott C

 

[Mike Treseler]

# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.

How do I fix this problem?

Remove 53 lines or buy a license.

-- Mike Treseler

 

[FPGA]

Remove 53 lines or buy a license.

      -- Mike Treseler

I want to add the ieee_proposed library which can be found at
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html . I
was
unsuccessfull in adding it the last time, so I just copy pasted the
files in the current work directory. Now, I am getting warnings that
# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.

I just found out that the packages in ieee_proposed that I added in
the work dir are huge and thats what is causing the problem. Please
suggest on how to add this library and also if I would still get the
same problems with the size even after adding the packages into a
library


Thanks

 

[Mike Treseler]

I just found out that the packages in ieee_proposed that I added in
the work dir are huge and thats what is causing the problem.

Glad you figured it out.

Please
suggest on how to add this library and also if I would still get the
same problems with the size even after adding the packages into a
library

It won't matter where the library is.
You are over the limit of the student license,
once you compile it into any library.
Pick a simpler project or call Mentor.

-- Mike Treseler

 

[FPGA]

Glad you figured it out.


It won't matter where the library is.
You are over the limit of the student license,
once you compile it into any library.
Pick a simpler project or call Mentor.

       -- Mike Treseler

Which tol do you suggest I use. I work on VHDL and Verilog. I need
something very basic.

 

[Dave Pollum]

Which tol do you suggest I use. I work on VHDL and Verilog. I need
something very basic.

Some companies, for example Xilinx, have full-featured products (i.e.
high-demo boards) at very low prices. Perhaps Mentor or some other
simulator company would be able to help you.
HTH
-Dave Pollum