Modelsim+Xilinx Block Ram Collision warnings

Discussion in 'VHDL' started by eko, May 15, 2008.

  1. eko

    eko

    Joined:
    Apr 16, 2008
    Messages:
    12
    Hey,

    these warnings drive me crazy, I use several (like more than 30) dual portblock rams, generated with the Xilinx CoreGenerator. All without port-enable-ports, means: no ena and enb, only wea and web :)

    Now, by default both address ports are initialized with zero...write enable for port B is set to 0 as well, still with EVERY simulation cycle (at least until the address changes - but that takes quite some time) I get a collision warning, e.g.

    # Time: 4 us Iteration: 14 Instance: /some/very/crazy/path/to/an/instance
    # ** Warning: blk_mem_gen_v2_6 WARNING: collision detected: A write address: 0000000000, B write address: 0000000000


    This drives me crazy, since this makes it nearly impossible to read the warnings thrown by other components that might be intresting for me. I already used the switch in the coregen promising to suppress warnings, but seems as if coregen and I disagree about what warnings we are talking about.

    Anyone with an idea?

    Thx in advance,


    e.
     
    eko, May 15, 2008
    #1
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