modelsim

[u_stadler]

hi

i have the following problem:

if i simulate my design in modelsim (xilinx edition) with the
behavioral model i can choose all my signals i use.
but if i simulate post translate a lot of the signal have different
names and some of them are split up (e.g. if i have a vector in my
design i have a different name for each bit). also if i try to add
signals that are in my designe it tells my it cant find them.

can anybody help me here please

thanks

 

[Mike Treseler]

but if i simulate post translate a lot of the signal have different
names and some of them are split up (e.g. if i have a vector in my
design i have a different name for each bit)

http://groups.google.com/groups?q=vhdl+gate+level+functional+static+timing+delay

-- Mike Treseler

 

[ajahn]

Hi,
well, there is not much help available for you. Depending on what your
synthesis tool does, you see more ore less of your original signals in
the gate level model. At the worst case, only the register outputs will
be left, logic will be optimized and the signals do not exist as such
anymore. If your hierarchy was flattened out, you usually get longer
names with the hierarchy path included in the signal name.
What you can do for simulation is, find the signals that you can still
identify in your design and assign them the original name. You can also
group together bits of a vector in a virtual signal and give the
virtual signal the original name.
You can then save them as a do-file and if you do some more tcl-coding,
you can even put the signals for functional and gate level sim into one
file and switch between them depending on the type of simulation (just
experiment a bit...)
But all of this is quite a bit of work and takes time for trying out.
Thus, I would only do this, if you have to run quite a lot of
simulations in gate-level and your gate level hierarchy does not change
a lot with every synthesis run (then you have to find the signals
again...).
I hope this gives you some ideas
Cheers,
Andreas

 

[canadianJaouk]

Hi,

You hierarchy is flatened during the implementation process. I believe
you should be able to see all the signals you want (plus lots of
useless ones) if you keep the hierarchy during the synthesis. Usin XST
(the xilinx synthesis tool), simply right click on "synthesize" and go
to properties. There will be an option there to keep the hierarchy.
Select yes and rerun you implementation. Make sure the property
display level is set to advance (otherwise you will not see the option
for keeping herarchy). The display level is a drop down option in
process property window (the one you are changing the hierarchy option
in). If you do this in Symplify, there are constraints you can put in
in the constraint file to keep the hierarchy, but i can't remember of
the top of my head. If you need, I will dig them up.

Hope this helps
-Jakub