Modification of Duty Cycle - Possible?

[Drew]

Hello all,

My input clock has 50% duty cycle and 40 MHz. I want to have output
clock of 25% duty cycle and 10MHz. Please let me know if anybody knows
the way to go.

Thanks,
Drew

 

[Pieter Hulshoff]

My input clock has 50% duty cycle and 40 MHz. I want to have output
clock of 25% duty cycle and 10MHz. Please let me know if anybody knows
the way to go.

Sounds like a simple counter running on your 40 MHz clock, running from 0 to
3, and decoding that as the output clock (1 vs 3) to get your 25% duty
cycle.

Something like:
PROCESS
VARIABLE cnt : integer RANGE 0 to 3 := 0;
BEGIN
WAIT UNTIL clk40 = '1';
cnt := (cnt + 1) MOD 4;
IF cnt = 0 THEN
clk10 <= '1'; -- 25%
ELSE
clk10 <= '0'; -- 75%
END IF;
IF reset = '1' THEN
-- reset settings
END IF;
END PROCESS;

Regards,

Pieter Hulshoff

 

[Charles M. Elias]

Hello all,

My input clock has 50% duty cycle and 40 MHz. I want to have output
clock of 25% duty cycle and 10MHz. Please let me know if anybody knows
the way to go.

Thanks,
Drew

Drew,

There is a simple way to do this (though it may not be the simplest
way). Make a 2-bit down counter and decode the zero count. The down
counter is a divide- by-4 for the 40 MHz clock. The decoded zero
count of this counter will have a frequency of 10 MHz and a 25% duty
cycle. If you don't like the idea of using a combinatorial output for
a clock, you can feed a d flip-flop with the decoder output. The d
flip-flop is clocked with the 40 MHz clock and its output is your 25%
duty cylcle 10 Mhz clock.

Best Regards,

Charles