module RGBtoYCrCb

[VHDL_HELP]

hi every body,
my problem is to simulate a module that make convert the 3 signals
Red , Green and Blue to Y,Cr and Cb
( transfom space color )
this program is correct with syntax but not synthetisable
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rgb is
Port ( clk : in STD_LOGIC;
reset: in STD_LOGIC;
r : in STD_LOGIC_VECTOR (10 downto 0);
g : in STD_LOGIC_VECTOR (10 downto 0);
b : in STD_LOGIC_VECTOR (10 downto 0);
y : out STD_LOGIC_VECTOR (21 downto 0);
cb: out STD_LOGIC_VECTOR (21 downto 0);
cr: out STD_LOGIC_VECTOR (21 downto 0));
end rgb;

architecture Behavioral of rgb is
signal s1,s2: bit_vector(10 downto 0);
signal yr,yg,yb,crr,crb,crg,cbr,cbb,cbg:STD_LOGIC_VECTOR (19 downto
0);
signal yy,cr1,cb1:STD_LOGIC_VECTOR (21 downto 0);
begin
-- component Y
yr <= "0100110010" * r;
yg <= "1001011001" * g;
yb <= "0001110100" * b;
yy <= yb + yg + yr;
-- component cr
s1 <= To_bitvector(r) srl 1;
crr <= "000000000" & To_StdLogicVector(s1);--decalage de 1 de r
crg <= "0110101101" * g;
crb <= "0001010011" * b;
cr1 <= crr - crg - crb;
-- component cb
cbr <= "0010101101" * r;
cbg <= "0101010011" * g;
s2 <= To_bitvector(b) srl 1;
cbb <= "000000000" & To_StdLogicVector(s2);--decalage de 1 de b
cb1 <= cbb - cbr - cbg;
-- the results
y <= yy;
cr <= cr1;
cb <= cb1;
end Behavioral;

 

[Jim Lewis]

VHDL_HELP,
For math, you should be using:
use IEEE.numeric_std.all ;

instead of:
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

It is unlikely that this is your fault.
Please give us the name and email of your professor so we
can help them understand which packages are the ones that
are part of an IEEE standard and which ones are not.

WRT to the rest of your problem, every result in VHDL has a
specific size. For multiply using array based math, the
size of the result is the sum of the size of the argument
arrays. Your errors will be further illuminated by reading
your code with this knowledge or by running it in a simulator
(which will either give your errors during compilation or
simulation).

You may find it helpful to read the paper, "VHDL Tricks of
the Trade" under the papers section of our website.

Good Luck,
Jim