MOORE Machine

Discussion in 'VHDL' started by seice.kao@gmail.com, Nov 10, 2007.

  1. Guest

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY MOORE IS
    PORT(Clock,RQA,RQB,TC,INIT : IN STD_LOGIC;
    Q,CEN,AKB,AKA,LDC : OUT STD_LOGIC);


    END ENTITY MOORE;

    ARCHITECTURE Behavior OF MOORE IS

    TYPE State_type IS (Q,CEN,AKB,AKA,LDC) ;
    SIGNAL current_state : state_type ;
    SIGNAL next_state : state_type ;

    BEGIN
    NEXT_State_PROC:pROCESS(current_state,INIT,RQA,RQB,TC)
    BEGIN
    CASE current_state IS
    WHEN wait_for_INIT => IF INIT='0' and RQA='0' and RQB='0'THEN
    next_state <= Q ;
    ELSIF INIT='1' and RQA='1' and RQB='0'THEN
    next_state <=AKA;
    ELSIF INIT='1' and RQA='1'THEN
    next_state <=AKA;
    ELSIF INIT='1' and RQA='0'THEN
    next_state <=LDC;
    ELSIF INIT='1'THEN
    next_state <=CEN;
    ELSIF INIT='1' and RQB='1'THEN
    next_state <=AKB;
    ELSIF INIT='1' and RQB='1'THEN
    next_state <=AKB;
    ELSIF INIT='1' and RQB='0'THEN
    next_state <=LDC;
    ELSIF INIT='1'THEN
    next_state <=CEN;
    ELSIF INIT='1'and TC='0' THEN
    next_state <=CEN;
    ELSIF INIT='1'and TC='1' THEN
    next_state <=Q;

    END IF;
    END CASE;
    END PROCESS NEXT_State_PROC;


    State_Register_Proc:pROCESS(Clock)

    BEGIN
    IF Clock'EVENT and Clock='1'THEN
    IF rising_edge(Clock)THEN
    IF INIT='0'THEN
    current_state<=wait_for_INIT;
    ELSE
    current_state<=next_state;
    END IF;
    END IF;
    END IF;
    END PROCESS State_Register_Proc ;


    END Behavior ;
     
    , Nov 10, 2007
    #1
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  2. > IF Clock'EVENT and Clock='1'THEN
    > IF rising_edge(Clock)THEN


    WTF?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

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    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Nov 10, 2007
    #2
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  3. KJ Guest

    "Jonathan Bromley" <> wrote in message
    news:...
    >> IF Clock'EVENT and Clock='1'THEN
    >> IF rising_edge(Clock)THEN

    >
    > WTF?


    What, you've never heard the saying "Measure twice, cut once"?

    Or perhaps it's a *reeeeeeally* fast rising clock edge?

    KJ
     
    KJ, Nov 11, 2007
    #3
  4. KJ Guest

    <> wrote in message
    news:...
    <snip>

    If you simply use one process you can do Moore with less.

    By the way, was there a point to this post?

    KJ
     
    KJ, Nov 11, 2007
    #4
  5. wrote:

    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    > USE ieee.std_logic_arith.all;


    Don't use std_logic_arith. Use numeric_std instead. If needed at all. In the
    code you posted it is not needed.

    >
    > ENTITY MOORE IS
    > PORT(Clock,RQA,RQB,TC,INIT : IN STD_LOGIC;
    > Q,CEN,AKB,AKA,LDC : OUT STD_LOGIC);
    >
    >
    > END ENTITY MOORE;
    >
    > ARCHITECTURE Behavior OF MOORE IS
    >
    > TYPE State_type IS (Q,CEN,AKB,AKA,LDC) ;


    Typo? Why try to use port signal names as enumeration type members?

    > SIGNAL current_state : state_type ;
    > SIGNAL next_state : state_type ;
    >
    > BEGIN
    > NEXT_State_PROC:pROCESS(current_state,INIT,RQA,RQB,TC)
    > BEGIN
    > CASE current_state IS
    > WHEN wait_for_INIT => IF INIT='0' and RQA='0' and RQB='0'THEN
    > next_state <= Q ;
    > ELSIF INIT='1' and RQA='1' and RQB='0'THEN
    > next_state <=AKA;
    > ELSIF INIT='1' and RQA='1'THEN
    > next_state <=AKA;
    > ELSIF INIT='1' and RQA='0'THEN
    > next_state <=LDC;
    > ELSIF INIT='1'THEN
    > next_state <=CEN;
    > ELSIF INIT='1' and RQB='1'THEN
    > next_state <=AKB;
    > ELSIF INIT='1' and RQB='1'THEN
    > next_state <=AKB;
    > ELSIF INIT='1' and RQB='0'THEN
    > next_state <=LDC;
    > ELSIF INIT='1'THEN
    > next_state <=CEN;
    > ELSIF INIT='1'and TC='0' THEN
    > next_state <=CEN;
    > ELSIF INIT='1'and TC='1' THEN
    > next_state <=Q;
    >
    > END IF;


    Hopeless repetition of INIT='1'. Use nested IFs:

    IF INIT='0' THEN
    IF RQA='0' and RQB='0' THEN
    next_state <= Q;
    ELSE
    next_state <= ...
    END IF;
    ELSE
    IF RQA='1' and RQB='0' THEN
    next_state <=AKA;
    ELSIF RQA='1' THEN
    next_state <=AKA;
    ...
    ELSE
    next_state <=...
    END IF;

    Make sure you either assign a default value to next_state or make sure
    next_state is assigned a value under all conditions. It not, you'll create
    a latch in this combinatorial process.

    And please sort out this mess of decoding the next state. Your transition to
    AKA happens if INIT='1' and RQA='1' and RQB='0',
    or if INIT='1' and RQA='1';
    That makes the term "and RQB='0'" redundant.

    For the rest: I give up.

    What is the meaning of this post anyway?

    Please post code that can be compiled, or post the code with the compilation
    error message and what you have tried already to solve it. And please form
    a decent question and put that in the subject.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, Nov 11, 2007
    #5
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