morre model

Discussion in 'VHDL' started by Keyvan Jamaleddin, Jul 14, 2005.

  1. Hi everyone,
    I got some errors while i was compiling the standard moore model for
    and i don't know what it means.

    Library ieee;
    Use ieee.std_logic_1164.all;
    Entity ali is
    Port (clk,reset,x :IN STD_LOGIC;
    Z :OUT STD_LOGIC);
    End ali;

    Architecture behavior of ali is
    Type statetype is (s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,
    s13,s14,s15,s16,s17,s18,s19,s20,s21,
    s22,s23,s24,s25,s26,s27);
    signal state : statetype;
    Begin
    IF reset = '1' then
    State<=state'LEFT;
    ELSIF (clk'event and clk = '1')then
    Case state is
    When s1 => if(x ='0')then
    State <=s2;
    Else
    State <=s1;
    End if;
    When s2 => if(x ='0')then
    State <=s3;
    Else
    State <=s8;
    End if;
    When s3 => if(x ='0')then
    State <=s4;
    Else
    State <=s8;
    End if;
    When s4 => if(x ='0')then
    State <=s5;
    Else
    State <=s8;
    End if;
    When s5=> if(x ='0')then
    State <=s6;
    Else
    State <=s8;
    End if;
    When s6 => if(x ='1')then
    State <=s7;
    Else
    State <=s1;
    End if;
    When s7 => if(x ='0')then
    State <=s1;
    Else
    State <=s1;
    End if;
    When s8 => if(x ='0')then
    State <=s9;
    Else
    State <=s1;
    End if;
    When s9 => if(x ='0')then
    State <=s10;
    Else
    State <=s13;
    End if;
    When s10 => if(x ='0')then
    State <=s11;
    Else
    State <=s8;
    End if;
    When s11 => if(x ='0')then
    State <=s12;
    Else
    State <=s8;
    End if;
    When s12 => if(x ='0')then
    State <=s1;
    Else
    State <=s8;
    End if;
    When s13 => if(x ='0')then
    State <=s14;
    Else
    State <=s1;
    End if;

    When s14 => if(x ='0')then
    State <=s2;
    Else
    State <=s15;
    End if;
    When s15 => if(x ='0')then
    State <=s16;
    Else
    State <=s13;
    End if;
    When s16 => if(x ='0')then
    State <=s17;
    Else
    State <=s13;
    End if;
    When s17 => if(x ='0')then
    State <=s3;
    Else
    State <=s18;
    End if;
    When s18 => if(x ='0')then
    State <=s1;
    Else
    State <=s1;
    End if;
    When s19 => if(x ='0')then
    State <=s20;
    Else
    State <=s1;
    End if;
    When s20 => if(x ='0')then
    State <=s21;
    Else
    State <=s13;
    End if;
    When s21 => if(x ='0')then
    State <=s22;
    Else
    State <=s8;
    End if;
    When s22 => if(x ='0')then
    State <=s23;
    Else
    State <=s8;
    End if;
    When s23 => if(x ='0')then
    State <=s1;
    Else
    State <=s8;
    End if;
    When s24 => if(x ='0')then
    State <=s1;
    Else
    State <=s25;
    End if;
    When s25 => if(x ='0')then
    State <=s1;
    Else
    State <=s26;
    End if;
    When s25 => if(x ='0')then
    State <=s1;
    Else
    State <=s26;
    End if;
    When s26 => if(x ='0')then
    State <=s27;
    Else
    State <=s1;
    End if;
    When s27 => if(x ='0')then
    State <=s1;
    Else
    State <=s1;
    End if;
    End Case;
    End IF;
    End Process;
    Begin
    Case state is

    When s7 =>
    Z <= "0000001";
    When s12 =>
    Z <= "0010000";
    When s18 =>
    Z <= "0101001";
    When s23 =>
    Z <= "0110000";
    When s27 =>
    Z <= "0111111";
    End Case;
    End Process;

    you can also e-mail me via

    thanks
     
    Keyvan Jamaleddin, Jul 14, 2005
    #1
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  2. Keyvan Jamaleddin

    Timo Alho Guest

    Keyvan Jamaleddin wrote:
    > Hi everyone,
    > I got some errors while i was compiling the standard moore model for
    > and i don't know what it means.
    >
    > Library ieee;
    > Use ieee.std_logic_1164.all;
    > Entity ali is
    > Port (clk,reset,x :IN STD_LOGIC;
    > Z :OUT STD_LOGIC);
    > End ali;
    >
    > Architecture behavior of ali is
    > Type statetype is (s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,
    > s13,s14,s15,s16,s17,s18,s19,s20,s21,
    > s22,s23,s24,s25,s26,s27);
    > signal state : statetype;
    > Begin


    something is missing here.

    "process (clk, reset)
    begin"

    might help?

    > IF reset = '1' then
    > State<=state'LEFT;
    > ELSIF (clk'event and clk = '1')then
    > Case state is
     
    Timo Alho, Jul 14, 2005
    #2
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