MSB in std_logic_vector

Discussion in 'VHDL' started by Dan, Nov 26, 2007.

  1. Dan

    Dan Guest

    Hi,

    I would like to get the most significant bit from a std_logic_vector, so
    that I can deduce if it's a signed or unsigned binary number. How can I do
    this?
    Dan, Nov 26, 2007
    #1
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  2. Dan

    Eric Smith Guest

    Dan wrote:
    > I would like to get the most significant bit from a std_logic_vector,
    > so that I can deduce if it's a signed or unsigned binary number. How
    > can I do this?


    If you know how the signal/type is declared, just index the appropriate
    bit. For isntance, if it is:

    signal foo: std_logic_vector (11 downto 0);

    you could use foo (11).

    In a situation where the declaration may not be visible, you can
    use the 'left attribute, e.g., foo (foo'left). That might be a good
    idea even when you know the index, as it makes it more clear that
    you're selecting the leftmost bit, and it won't break if the width
    of the signal changes.

    You can also use IEEE.numeric_std, and cast the std_logic_vector
    into the type "signed", and then use a numeric comparison against
    0 (or other numeric literals).
    Eric Smith, Nov 27, 2007
    #2
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  3. Dan

    KJ Guest

    "Dan" <> wrote in message
    news:fifm0r$nvq$-data.net...
    > Hi,
    >
    > I would like to get the most significant bit from a std_logic_vector, so
    > that I can deduce if it's a signed or unsigned binary number. How can I do
    > this?


    If the vector is representing a signed number then you'll be much farther
    ahead if you use the ieee.numeric_std package to work with instead.

    But the straightforward way to get the MSB of a vector 'vec' without having
    to hardcode a particular bit number (which is subject to change) is the
    following

    vec_msb <= vec(vec'left);

    KJ
    KJ, Nov 27, 2007
    #3
  4. Dan wrote:

    > I would like to get the most significant bit from a std_logic_vector, so
    > that I can deduce if it's a signed or unsigned binary number. How can I
    > do this?


    A std_logic_vector is just an array of bits.
    If I happen to know that the value is signed, the
    msb is usually the sign bit, but I certainly can't
    determine the type by the value of the msb.

    -- Mike Treseler
    Mike Treseler, Nov 27, 2007
    #4
  5. Dan

    Andy Guest

    On Nov 26, 7:11 pm, Mike Treseler <> wrote:
    > Dan wrote:
    > > I would like to get the most significant bit from a std_logic_vector, so
    > > that I can deduce if it's a signed or unsigned binary number. How can I
    > > do this?

    >
    > A std_logic_vector is just an array of bits.
    > If I happen to know that the value is signed, the
    > msb is usually the sign bit, but I certainly can't
    > determine the type by the value of the msb.
    >
    > -- Mike Treseler


    Dan,

    What Mike is trying to say, is that your original question states you
    want to determine whether a value is signed or unsigned. Those are
    representations (types), not values. If you meant "negative or
    positive", and you know the representation is signed (obviously,
    otherwise there would be no negative values to consider), then, yes
    the MSB will tell you that. Otherwise, the MSB value tells you nothing
    about representation.

    This is the reasoning behind the numeric_std package and its
    definitions of types signed and unsigned: because it is impossible for
    VHDL to know the numeric representation of an SLV. Defining the data
    as signed or unsigned (by putting it in the appropriate type of signal
    or variable) allows VHDL to automatically select the appropriate
    operator version to ensure that the results are arithmetically
    correct.

    Andy
    Andy, Nov 27, 2007
    #5
  6. Dan

    Dan Guest

    Thanks all

    Dan,


    "Andy" <> wrote in message
    news:...
    > On Nov 26, 7:11 pm, Mike Treseler <> wrote:
    >> Dan wrote:
    >> > I would like to get the most significant bit from a std_logic_vector,
    >> > so
    >> > that I can deduce if it's a signed or unsigned binary number. How can I
    >> > do this?

    >>
    >> A std_logic_vector is just an array of bits.
    >> If I happen to know that the value is signed, the
    >> msb is usually the sign bit, but I certainly can't
    >> determine the type by the value of the msb.
    >>
    >> -- Mike Treseler

    >
    > Dan,
    >
    > What Mike is trying to say, is that your original question states you
    > want to determine whether a value is signed or unsigned. Those are
    > representations (types), not values. If you meant "negative or
    > positive", and you know the representation is signed (obviously,
    > otherwise there would be no negative values to consider), then, yes
    > the MSB will tell you that. Otherwise, the MSB value tells you nothing
    > about representation.
    >
    > This is the reasoning behind the numeric_std package and its
    > definitions of types signed and unsigned: because it is impossible for
    > VHDL to know the numeric representation of an SLV. Defining the data
    > as signed or unsigned (by putting it in the appropriate type of signal
    > or variable) allows VHDL to automatically select the appropriate
    > operator version to ensure that the results are arithmetically
    > correct.
    >
    > Andy
    Dan, Nov 30, 2007
    #6
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