mulitdimensional array at port configurations...

[Dkthechamp]

Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

Thanks,

Deepak

 

[Paul Uiterlinden]

Hi,

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

Put the type declaration in a package and make the contents of that package
visible for the entity. That is, put a use clause with that package (e.g.
use work.pkg.all in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array (or
alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do some
slicing magic in the architecture.

 

[Jonathan Bromley]

How can we declare a multidimensional array, while declaring the port
of an entitity? (2 D in specific of std_logic_vector type). The input
is of 'x' bit each and there are n such inputs.

In Verilog-2001, you can't.

Paul's post on packages is right for SystemVerilog.

If you don't have SystemVerilog tools, give up and use VHDL
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Dkthechamp]

Put the type declaration in a package and make the contents of that package
visible for the entity. That is, put a use clause with that package (e.g.
use work.pkg.all in front of the entity declaration.

This of course implicates that the sizes of your multi dimensional array (or
alternatively, array of arrays or vectors) are fixed.

If you want them unconstrained, then the only solution is to use an
unconstrained one dimensional array (such as std_logic_vector) and do some
slicing magic in the architecture.

thanks Paul, will this solution be synthesizable !!!

 

[Dkthechamp]

thanks Paul, will this solution be synthesizable !!!

i am using already using VHDL

 

[Jonathan Bromley]

If you don't have SystemVerilog tools, give up and use VHDL

Oops, sincere apologies, wrong newsgroup ;-) Of course Paul is right
that in VHDL you need a package. A nasty case of typing at higher
speed than thinking.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Andy]

If you can live with an array of arrays, the outer array can be
unconstrained, the inner one must be constrained, in the current
version of vhdl. An advantage of arrays of arrays is that you can use
slices or elements of the outer array, and you can access slices or
elements of one element of the outer array. In a lot of hardware
circuit descriptions, this is very beneficial.

Usually when I define a type that is used in a port definition on an
entity, I put the package containing the type definition at the top of
the file for the entity. That way, if the entity is compiled, the
package is too, and both are visible (with the appropriate use
statement for the package).

In the future, generics on packages, and arrays of unconstrained
arrays will make this a lot more convenient.

Andy

 

[Paul Uiterlinden]

thanks Paul, will this solution be synthesizable !!!

As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

 

[Paul Uiterlinden]

Oops, sincere apologies, wrong newsgroup ;-) Of course Paul is right
that in VHDL you need a package. A nasty case of typing at higher
speed than thinking.

It seems your brain is written in Verilog. The dead give away of course are
the race conditions! ;-)

Don't let that stop you posting though. The technical insights combined with
humor in your postings is a rare combination that I've grown to appreciate
very much.

 

[bullsandeagles]

As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

sir..
are arrays of vector synthesizeable????
just like if i declare something like
[7:0]temp [0:255] ?????

 

[Andy]

As far as I know it is. The only problem perhaps is that it cannot not be
used at top level. But then again, this is unknown territory for me, as I
hardly ever bother with synthesis.

sir..
are arrays of vector synthesizeable????
just like if i declare something like
[7:0]temp [0:255] ?????

Yes.

Andy