Multi-source on Integers in Concurrent Assignment.

Discussion in 'VHDL' started by sam.green, Oct 6, 2008.

  1. sam.green

    sam.green

    Joined:
    Jun 23, 2008
    Messages:
    4
    Hello,

    I am using Xilinx ISE 10.1 to synthesize some code that simulates correctly. This is my first nontrivial (to me) FPGA/digital design. I am getting the error:

    Multi-source on Integers in Concurrent Assignment.​

    By commenting out clk_counter := clk_counter + 1, the error goes away (although there are different errors that appear).

    My full code can be found here.

    A Word document explaining what I am trying to do is here. In short, I am trying to build a serial to parallel radio decoder.

    What am I doing wrong in the following code?

    -- clock/timing process
    process(clk)
    begin
    -- asynchronous reset
    if (reset = '1') then
    current_state <= reset_st;
    elsif rising_edge(clk) then
    -- wrapping counter that keeps track of FPGA clocks
    clk_counter := clk_counter + 1; -- fail
    debug_current_counter <= clk_counter;

    -- used for time-outs of polling in the state machine
    -- fsm sets bit_poll and three_half_bit_time
    if (bit_poll = '1' and clk_counter = three_half_bit_time) then
    current_state <= store_bit_st;
    else
    current_state <= next_state;
    end if;

    end if;
    end process;

    Thanks!
    Sam
     
    sam.green, Oct 6, 2008
    #1
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  2. sam.green

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi Sam

    I believe that the missing reset in the sensitivity list could be one problem
    BUT - even if your using Shared Variables must there only be ONE process which controls this variable

    Your welcome
    Jeppe
     
    jeppe, Oct 7, 2008
    #2
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  3. sam.green

    sam.green

    Joined:
    Jun 23, 2008
    Messages:
    4
    Hi Jeppe,

    Thank you for your response. That was my problem; I was assigning clk_counter from two processes.

    As for the reset not being in the sensitivity list, doesn't that just mean that I have a synchronous reset. Can it cause problems the way it is currently written?
     
    sam.green, Oct 7, 2008
    #3
  4. sam.green

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    I believe the Tools will reconize your Asyncrone Clear (or Reset if you like) even without the missing signal

    Jeppe
     
    jeppe, Oct 8, 2008
    #4
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