# Multi Valued logic simulation using VHDL?

Discussion in 'VHDL' started by Guru Prasad, Feb 20, 2004.

Hi!

I have taken on a project of benchmarking the relative performance of
a binary ALU Vs a ternary ALU. I was wondering if I could use VHDL to
program a simple ALU that does multiplication, addition and division
for multi-valued logic and if so, could someone point me to recources

thanks.

2. ### Guest

Am Samstag, 22. September 2012 23:55:43 UTC+2 schrieb ashw_pict:
> yes you can simulate ternary ALU.you have to refer to the paper by a.p.dhande,r.c.jaiswal and s.s. dudam title ternary logic simulator using vhdl.
>
>
>
> --http://compgroups.net/comp.lang.vhdl/multi-valued-logic-simulation-using-vhdl/367352

Hi,
an intersting paper, since they provide the source code for their ternary types and operators.
But one thing makes me wonder.
To my understanding the ternary logic type should improve arithmetic functions.
In the paper the ternary type uses {0, Z, 1}.
So, when I get some logic result, is Z interpreted as 0.5?
Why didn't they create a new type {0 1 2} and overload the operators and functions for it, just like it is done for the std_logic type?

Have a nice simulation
Eilert
, Sep 28, 2012

3. ### Lokesh KannaGuest

On Saturday, February 21, 2004 12:13:12 AM UTC+5:30, Guru Prasad wrote:
> Hi!
>
> I have taken on a project of benchmarking the relative performance of
> a binary ALU Vs a ternary ALU. I was wondering if I could use VHDL to
> program a simple ALU that does multiplication, addition and division
> for multi-valued logic and if so, could someone point me to recources
>
> thanks.

hai guru,
I hv planned to do the same project that u did...Though u hv done years back,help me by sending some links where we can find the sample codes for ternary MVL operation. .