Multidimensional generic vhdl

S

Salman

Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman
 
M

Mike Treseler

Salman said:
I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc
taking the form mux_A_Bx1
where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this?

It's possible, but not necessary if you have quartus or ise.
Muxes will be inferred as needed from conditional statements.

Notice that the netlist here:
http://home.comcast.net/~mike_treseler/uart.pdf
has about 45 muxes of various sizes.

Notice that the source code here:
http://home.comcast.net/~mike_treseler/uart.vhd
that generated the netlist does not
even mention a mux.


-- Mike Treseler
 
A

Andy

Salman said:
Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman

The only way I've seen it done is to have a single vector as the
input(s), and slice it up internally. I've changed b to be the number
of bits in the select line (2**b inputs)

generic (a, b ; natural);
port (input : in std_logic_vector(a * 2**b - 1 downto 0);
select : in std_logic(b - 1 downto 0);
output : out std_logic_vector(a - 1 downto 0));

There is a proposed update to vhdl to allow arrays of unconstrained
arrays, which would allow you to create a type that could be used for
the input port the way you envisioned it.

Andy
 
J

Jim Lewis

Salman,
Is this a homework problem? I will give you some
good hints either way.

Since this is a small simple block of combinational
logic, I would use a subprogram with unconstrained arrays
(to allow the width to adjust based on inputs) and
initialize the inputs (so if you don't use them they
default to 0). The only thing you need to constrain
is the multiplexor selector (case statement requires
a locally static type).

This approach will reduce your problem size to creating
mux2, mux4, mux8, ... If you truely want it flexible,
I would create it for std_logic and std_logic_vector.
> Synthesis?
I have not tried initialized subprogram inputs on
enough synthesis tools yet to say it is portable
across synthesis tools, the rest though should
not be a problem.




Cheers,
Jim


Hi,

I'm trying to create a generic mux that takes 2 parameters..such as
mux_2_2x1 or mux_8_8x1, etc

taking the form mux_A_Bx1

where the parameters would be A the width of the inputs and B the
number of inputs...and there always is 1 output....the problem is : how
do you have a parameterizable number of input ports and how do you code
this? Is something like this synthesizable?

Salman


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Joined
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Hello,

I would like to start with saying that I am very new to this... but perhaps that's needless because my questions clear this up anyway :)

So is setting the number of inputs/outputs through a generic parameter impossible with the current VHDL standard? I hope I've misunderstood.

It's possible, but not necessary if you have quartus or ise.
I have both of them installed and atm use Quartus as the code-editor and verificator. After code looks OK and Quartus doesen't complain, I try to simulate in ModelSim.

I wrote a code for a DEMUX with variable number of inputs (consisting of std_logic_vector (3:0) and (5:0), don't ask why).

Quatrus is happy with the design, but ModelSim complains that:
** Error: C:/altera/72sp3/quartus/projects/inp_sel/inp_sel_tb.vhd(52): Actual (aggregate) for formal "in_4_bits" is not a static signal name.
** Error: C:/altera/72sp3/quartus/projects/inp_sel/inp_sel_tb.vhd(53): Actual (aggregate) for formal "in_6_bits" is not a static signal name.

the actual lines are:
in_4_bits => (in_4_bits_0, in_4_bits_1, in_4_bits_2, in_4_bits_3, in_4_bits_4),
in_6_bits => (in_6_bits_0, in_6_bits_1, in_6_bits_2, in_6_bits_3, in_6_bits_4),

What's the problem, what should I do differently?

inp_sel_tb.vhd :
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use work.TIBC_typedef.all;

entity inp_sel_tb is

	port
	(
		set_what	: in integer range 0 to 5;
		
		in_4_bits_0	: in std_logic_vector (3 downto 0);
		in_6_bits_0	: in std_logic_vector (5 downto 0);
		
		in_4_bits_1	: in std_logic_vector (3 downto 0);
		in_6_bits_1	: in std_logic_vector (5 downto 0);
		
		in_4_bits_2	: in std_logic_vector (3 downto 0);
		in_6_bits_2	: in std_logic_vector (5 downto 0);
		
		in_4_bits_3	: in std_logic_vector (3 downto 0);
		in_6_bits_3	: in std_logic_vector (5 downto 0);
		
		in_4_bits_4	: in std_logic_vector (3 downto 0);
		in_6_bits_4	: in std_logic_vector (5 downto 0);
		
		out_4_bits	: out std_logic_vector (3 downto 0);
		out_6_bits	: out std_logic_vector (5 downto 0)
	);
	
end entity inp_sel_tb;

architecture tb of inp_sel_tb is
	component inp_sel is
		generic
		(NR_OF_INPUTS : integer := 2);
		port
		(
			set_what	: in integer range 0 to (NR_OF_INPUTS - 1);
			in_4_bits	: in inputs_4;
			in_6_bits	: in inputs_6;
			out_4_bits	: out std_logic_vector (3 downto 0);
			out_6_bits	: out std_logic_vector (5 downto 0)
		);
	end component;
	
begin
	DUT: inp_sel
		generic map (5)
		port map
		(
			set_what	=> set_what,
			in_4_bits	=> (in_4_bits_0, in_4_bits_1, in_4_bits_2, in_4_bits_3, in_4_bits_4),
			in_6_bits	=> (in_6_bits_0, in_6_bits_1, in_6_bits_2, in_6_bits_3, in_6_bits_4),
			out_4_bits	=> out_4_bits,
			out_6_bits	=> out_6_bits
		);
end tb;
inp_sel.vhd :
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use work.TIBC_typedef.all;

entity inp_sel is

	generic
	(
		NR_OF_INPUTS : integer := 2
	);
	
	port
	(
		set_what	: in integer range 0 to (NR_OF_INPUTS - 1);
		in_4_bits	: in inputs_4;
		in_6_bits	: in inputs_6;
		out_4_bits	: out std_logic_vector (3 downto 0);
		out_6_bits	: out std_logic_vector (5 downto 0)
	);

end entity;

architecture behaviour of inp_sel is
begin
	out_4_bits <= in_4_bits(set_what);
	out_6_bits <= in_6_bits(set_what);
end behaviour;
TIBC_typedef.vhd :
Code:
library IEEE;
use IEEE.std_logic_1164.all;

package TIBC_typedef is

	constant NR_OF_INPUTS : positive := 2;
	type inputs_4 is array (0 to NR_OF_INPUTS - 1) of std_logic_vector (3 downto 0);
	type inputs_6 is array (0 to NR_OF_INPUTS - 1) of std_logic_vector (5 downto 0);
	
end package TIBC_typedef;

package body TIBC_typedef is
end TIBC_typedef;

Thank you, helpful people!
 
Last edited:

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