multiple asychronous resets

Discussion in 'VHDL' started by Ruth, Jun 26, 2003.

  1. Ruth

    Ruth Guest

    Hi,

    Are there any problems with having more than one asynchronous reset? I
    assumed that the synthesis tool just added an 'or' gate in front of the
    reset on the FF, but I've ben told recently that this is not necessarily the
    case and that it can cause problems. Can anyone shed any light on what
    these might be please?

    process (reset, clk, o_mreset)
    begin
    if (reset = '1') or (o_mreset = '1') then
    dummy <= '0';
    elsif rising_edge(slow_clk) then
    if control = '1' then
    dummy <= i_dummy;
    end if;
    end if;
    end process;

    Thanks

    Ruth
    Ruth, Jun 26, 2003
    #1
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  2. Ruth wrote:
    >
    > Hi,
    >
    > Are there any problems with having more than one asynchronous reset? I
    > assumed that the synthesis tool just added an 'or' gate in front of the
    > reset on the FF, but I've ben told recently that this is not necessarily the
    > case and that it can cause problems. Can anyone shed any light on what
    > these might be please?
    >
    > process (reset, clk, o_mreset)
    > begin
    > if (reset = '1') or (o_mreset = '1') then
    > dummy <= '0';
    > elsif rising_edge(slow_clk) then
    > if control = '1' then
    > dummy <= i_dummy;
    > end if;
    > end if;
    > end process;


    The result of this depends on your target architecture.

    If you're targeting an ASIC, you'll probably get exactly what you
    expect.

    However, FPGAs can be quite different. Xilinx (and other) FPGAs have a
    global reset net that is routed directly to all FFs. However, if you use
    *any* logic on the reset line, other than inversions, the synthesis
    tools will kick all resets off the global net and onto regular routing
    resources. There are Xilinx app notes and/or answer records that discuss
    this. Xilinx recommends against using the dedicated reset net in bigger
    parts due to timing issues but in many designs this is not an issue and
    it does save routing resources.

    This is really an implementation issue not a VHDL issue and you should
    ask in comp.arch.fpga instead.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jun 26, 2003
    #2
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