multiple clock domains issues

Discussion in 'VHDL' started by JK, Mar 21, 2007.

  1. JK

    JK Guest

    Few doubts I would like to get clarified,

    1. Weather synchronizers are required for control signals only or for
    data signals also?

    2. Internal to FPGA, suppose 2 different clock domains are there - do
    signals crossing from one clock domain
    to another need synchronizers? or can we avoid synchronizers by
    applying some constraints?
    If yes, what are these contraints(in xilinx)?

    3. How can we decide on a false path? suppose one signal is crossing
    from one clock domain to another can be
    declared as a false path?

    4. Is it OK to have negative hold time(<1 ns) in timing report? can we
    ignore this timing violation safely?

    5. What is the difference between clock jitter & clock skew?
    With Xilinx DCMs, I need Clk2x, Clk2x<180, Clk2x<270 & Clk4x.
    So, with no other option, I am going for cascaded DCMs.
    In this kind of situations, what best we can do to avoid/minimize
    clock skew problems?

    Regards,
    JK
    JK, Mar 21, 2007
    #1
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  2. Mike Treseler, Mar 24, 2007
    #2
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