Multiple loop GENERATE

Discussion in 'VHDL' started by Ricewind, Feb 11, 2010.

  1. Ricewind

    Ricewind

    Joined:
    Jan 28, 2010
    Messages:
    4
    Hi, I need to make a Generate statement depending on 2 variables.

    I have tried to code it this way but it does not work:

    registro8bits: FOR i IN 1 TO numcol
    FOR j IN 0 TO numfil GENERATE
    registrazo: registrode8bits port map (reloj_clk_1, reloj_ce_1, Reset, intermedia(j,i-1),intermedia(j,i));
    Salida(j,i)<=intermedia(j,i);
    END GENERATE;
    END loop;

    any ideas?

    Thank you in advance
    Ricewind, Feb 11, 2010
    #1
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  2. Ricewind

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    - the outer loop has incorrect syntax
    - each generate line needs a label

    Try this:
    Code:
    registro8bits: FOR i IN 1 TO numcol generate
    inner: FOR j IN 0 TO numfil GENERATE
    registrazo: registrode8bits port map (reloj_clk_1, reloj_ce_1, Reset, intermedia(j,i-1),intermedia(j,i));
    Salida(j,i)<=intermedia(j,i);
    END GENERATE inner;
    END generate registro8bits;
    
    joris, Feb 11, 2010
    #2
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  3. Ricewind

    Ricewind

    Joined:
    Jan 28, 2010
    Messages:
    4
    Thank you very much, it works fine : D
    Ricewind, Feb 11, 2010
    #3
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