Multiple Reset Inputs

A

Analog_Guy

I generally implement resets with asynchronous assertion and
synchronous de-assertion. With a single reset, this is simple.
However, what happens if there are multiple reset inputs but I only
want one internal reset?

I was always under the impression that one should not have any
combinational logic in the asynchronous reset path, as it could lead
to static hazards (and reset glitches). So, how do you combine two
resets into one without using combinational logic somewhere?

I was thinking of two scenarios:
1. AND the two resets coming into the FPGA, and connect to the
asynchronous reset of a synchronizer. The output of the synchronizer
is the single internal reset.
2. Individually synchronize the two resets coming into the FPGA (note
that each reset input feeds the asynchronous reset of the
synchronizer). AND the output of each of the synchronizers and feed
this single signal into the asynchronous reset of a final flip-flop.
The output of this flip-flop is the single internal reset.

In both cases we achieve asynchronous assertion and synchronous de-
assertion ... however, in both cases there is combinational logic in
the asynchronous reset path.

Any suggestions how these multiple resets should be combined?
 
K

KJ

I was always under the impression that one should not have any
combinational logic in the asynchronous reset path, as it could lead
to static hazards (and reset glitches).  

That would be the situation if you're trying to *avoid* resetting
something because of a transient condition. An example would be if
you're supposed to reset something when you've decoded a particular
processor address. Simple combinatorial logic then might
inadvertantly generate a reset pulse that is not wanted because of
transient conditions on the address bus, propagation delays through
logic paths, etc.
So, how do you combine two
resets into one without using combinational logic somewhere?

By or-ing them together.
I was thinking of two scenarios:
1. AND the two resets coming into the FPGA, and connect to the
asynchronous reset of a synchronizer.  The output of the synchronizer
is the single internal reset.

I think you mean 'or', not 'and'. But other than that, what you've
described would be correct.
2. Individually synchronize the two resets coming into the FPGA (note
that each reset input feeds the asynchronous reset of the
synchronizer).  AND the output of each of the synchronizers and feed
this single signal into the asynchronous reset of a final flip-flop.
The output of this flip-flop is the single internal reset.

Again, except for saying 'and' rather than 'or', what you've descirved
would work here also. It would consume more resources, but it would
work, no better, no worse than #1.
In both cases we achieve asynchronous assertion and synchronous de-
assertion ... however, in both cases there is combinational logic in
the asynchronous reset path.

But that combinatorial logic that you're talking about is not a
problem because in this situation you're not trying to prevent a false
logic reset from happening.

It's good to question things one has 'always done' every now and then
to refresh yourself on fundamentally why you do such things.

Kevin Jennings
 
J

jacko

remember the two flip flop rule one for async to sync, and one to
leave one propergation interval for what? seems almost silly! maybe
its a feedback reset reduction fan out technique.
 
A

Andy

remember the two flip flop rule one for async to sync, and one to
leave one propergation interval for what? seems almost silly! maybe
its a feedback reset reduction fan out technique.

The 2nd flop is to reject a potential metastable pulse from the 1st
synchronizing flop. It is not necessary if the destination is another
flop on the same or related clock, and you have sufficiently extra
timing margin to get there (a few extra nanoseconds will buy an eon in
MTBF in most FPGAs).

Andy
 

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