Multiple source tolerated by Modelsim

Discussion in 'VHDL' started by ALuPin, Jul 9, 2004.

  1. ALuPin

    ALuPin Guest

    Hi,

    I have the following question:

    Given one signal "l_data" which is created in a clock synchronous process.

    As an concurrent assignment I have the following:

    l_data_help <= l_data;
    l_data_help(4) <= NOT l_data(4);

    When compiling that Modelsim does NOT show any warning although it is
    a multiple source.

    Am I right?

    Rgds
     
    ALuPin, Jul 9, 2004
    #1
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  2. On 9 Jul 2004 06:51:28 -0700, (ALuPin) wrote:

    >Given one signal "l_data" which is created in a clock synchronous process.
    >
    >As an concurrent assignment I have the following:
    >
    >l_data_help <= l_data;
    >l_data_help(4) <= NOT l_data(4);
    >
    >When compiling that Modelsim does NOT show any warning although it is
    >a multiple source.
    >
    >Am I right?


    If l_data_help is a STD_LOGIC_VECTOR then there is no problem with
    multiple drivers on it; however, your code will always drive it to
    'U' or 'X'.

    Similarly, if the elements of l_data_help are of ANY resolved type,
    your code is legal (but probably not useful).

    On the other hand, if the elements of l_data_help are of unresolved
    type, the simulator should detect the error at elaboration time.
    At compile time it is NOT required to detect the error, although
    it wll probably give a warning in this case where both drivers
    exist in the same design unit.

    As an experiment, try re-defining l_data and l_data_help to be
    STD_ULOGIC_VECTOR instead of STD_LOGIC_VECTOR.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Jul 9, 2004
    #2
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  3. Jonathan Bromley a écrit:

    > On the other hand, if the elements of l_data_help are of unresolved
    > type, the simulator should detect the error at elaboration time.
    > At compile time it is NOT required to detect the error, although
    > it wll probably give a warning in this case where both drivers
    > exist in the same design unit.
    >
    > As an experiment, try re-defining l_data and l_data_help to be
    > STD_ULOGIC_VECTOR instead of STD_LOGIC_VECTOR.


    ModelSim won't give any warning or error at compile time (I've already
    posted about this a few weeks ago)
    I didn't know at the time that the error detection was due at
    elaboration time.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Jul 9, 2004
    #3
  4. On Fri, 09 Jul 2004 16:57:55 +0200, Nicolas Matringe
    <> wrote:

    >Jonathan Bromley a écrit:
    >

    [concerning multiple sources on a signal)
    >
    >ModelSim won't give any warning or error at compile time (I've already
    >posted about this a few weeks ago)


    Sorry Nicolas, I missed your post on that issue.

    Hmmm... A few days ago I was doing some complicated and messy
    stuff with "generate", and the compiler warned me that there
    MIGHT be multiple sources... it was right, until I fixed the
    code :) but even when my "generate" code was correct, I still
    got the warning. In this case, of course, there was no error
    at elaboration.

    >I didn't know at the time that the error detection was due at
    >elaboration time.


    There are many possible errors that cannot be detected until
    elaboration. On the other hand, some simple cases could
    in principle be detected earlier. I guess it's just a question
    of how hard the compiler is prepared to work, to detect some
    of these cases.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Jul 9, 2004
    #4
  5. Jonathan Bromley a écrit:
    > On Fri, 09 Jul 2004 16:57:55 +0200, Nicolas Matringe
    > <> wrote:
    > [concerning multiple sources on a signal)
    >>ModelSim won't give any warning or error at compile time (I've already
    >>posted about this a few weeks ago)

    > Sorry Nicolas, I missed your post on that issue.


    The whole thread is here (but I'm sure you already know how to find it ;o)
    http://tinylink.com/?KWoPIItiUt


    > There are many possible errors that cannot be detected until
    > elaboration. On the other hand, some simple cases could
    > in principle be detected earlier. I guess it's just a question
    > of how hard the compiler is prepared to work, to detect some
    > of these cases.


    Michael Riepe pointed that some cases couldn't be detected until
    elaboration, for example when using generic parameters:

    >>> Quoted text:

    If the signals assigned to don't have locally static names, it
    will be impossible to detect multiple sources before elaboration:

    generic (index : integer := 1);
    -- ...
    signal sig : std_ulogic_vector(...);
    -- ...
    sig(0) <= '1'; -- locally static
    sig(index) <= '0'; -- not locally static

    During elaboration, `index' may or may not become 0.
    <<< end of quoted text.


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Jul 12, 2004
    #5
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