Multiplexer

Discussion in 'VHDL' started by john, Jun 14, 2006.

  1. john

    john Guest

    Hi,

    I am trying to build a multiplexer. It has two select lines . When its
    '11', it selects A when its '00' it selects B . Now, i do not want to
    select anything else and maintain A or B at its output even the select
    line changes to anything else like "01" or "10"... How can I do that .
    I saw may examples and found that { when others => A <= ( others =>
    'X' ) }

    John.
    john, Jun 14, 2006
    #1
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  2. john

    Rtafas Guest

    Have you ever considered reading some digital systems book and/or heard
    about flip-flops or latches? VHDL and it's "a lot more understandable"
    with this knowledge. You shoud *really* do this.

    You must use a process to save information. Flip-flops and latches are
    generetade only this way. Something like:

    process(clk)
    begin
    if clk'event and clk = '1' then
    if sel_lines = "11" then
    out <= a;
    elsif sel_lines = "00" then
    out <= b;
    end if;
    end if;
    end process;

    What you have been reading was about assyncronous logic (gates). It
    won't save any value for you.

    Regards,

    Ricardo

    john escreveu:

    > Hi,
    >
    > I am trying to build a multiplexer. It has two select lines . When its
    > '11', it selects A when its '00' it selects B . Now, i do not want to
    > select anything else and maintain A or B at its output even the select
    > line changes to anything else like "01" or "10"... How can I do that .
    > I saw may examples and found that { when others => A <= ( others =>
    > 'X' ) }
    >
    > John.
    Rtafas, Jun 14, 2006
    #2
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  3. john

    john Guest

    Hi Rtafas,
    Thanks for ur reply! Have you ever considered to read writers like
    shakespear or milton or books like Bible or Quran or intorduction to
    ethics. If not, you should read them, before you die. because
    engineering or sciences , did take alot of common sense from your
    brain.
    I had a simple confusion about the mux. I apologize that I put it on
    the group. But you do not have to answer it if you think its too simple
    for u. why did u bother to answer it. let it answer by other people.
    Regards
    John
    john, Jun 14, 2006
    #3
  4. Mike Treseler, Jun 14, 2006
    #4
  5. john

    Rtafas Guest

    Hey, calm down buddy. You sound a little nervous.

    You had a doubt. I've made some suggestion, and it was a very good and
    important one. You really should consider reading a good digital
    systems book (that is not an offense, its a resonable hint due to your
    question: you do not seem experienced in digital design and if so,
    sorry then). Then I´ve replied your question with a piece of code and
    I gave you a good explanation. No need for flaming.

    Maybe you should take things with a more technical view than a personal
    one, because no one is here to flame you. I won't give you a hug after
    answering any question. :p

    Sorry for the joke, regards

    RTafas

    john escreveu:

    > Hi Rtafas,
    > Thanks for ur reply! Have you ever considered to read writers like
    > shakespear or milton or books like Bible or Quran or intorduction to
    > ethics. If not, you should read them, before you die. because
    > engineering or sciences , did take alot of common sense from your
    > brain.
    > I had a simple confusion about the mux. I apologize that I put it on
    > the group. But you do not have to answer it if you think its too simple
    > for u. why did u bother to answer it. let it answer by other people.
    > Regards
    > John
    Rtafas, Jun 14, 2006
    #5
  6. john

    john Guest

    Hi,
    I am sorry that I sounded angry or flaming. I do believe that u do need
    to study those books and writers atleast once in ur lifetime for ur own
    good. The materail, I mentioned is easily available at barnes and
    nobles or any book shop in any counrty of the world. i will recommed
    Hamlet by shakespear and bible. Please read them. Thanks again for ur
    piece of code and reply.
    Bye
    John
    john, Jun 14, 2006
    #6
  7. john

    Andy Guest

    You do not have to have an _explicit_ process to save information:

    q <= d when rising_edge(clk); -- flip flop

    q <= d when en = '1'; -- latch

    output <= a when sel = '11' else b when sel = '00'; -- mux + latch

    That said, latches are not generally a good idea in ASICs and FPGAs.

    Andy


    Rtafas wrote:
    > Have you ever considered reading some digital systems book and/or heard
    > about flip-flops or latches? VHDL and it's "a lot more understandable"
    > with this knowledge. You shoud *really* do this.
    >
    > You must use a process to save information. Flip-flops and latches are
    > generetade only this way. Something like:
    >
    > process(clk)
    > begin
    > if clk'event and clk = '1' then
    > if sel_lines = "11" then
    > out <= a;
    > elsif sel_lines = "00" then
    > out <= b;
    > end if;
    > end if;
    > end process;
    >
    > What you have been reading was about assyncronous logic (gates). It
    > won't save any value for you.
    >
    > Regards,
    >
    > Ricardo
    >
    > john escreveu:
    >
    > > Hi,
    > >
    > > I am trying to build a multiplexer. It has two select lines . When its
    > > '11', it selects A when its '00' it selects B . Now, i do not want to
    > > select anything else and maintain A or B at its output even the select
    > > line changes to anything else like "01" or "10"... How can I do that .
    > > I saw may examples and found that { when others => A <= ( others =>
    > > 'X' ) }
    > >
    > > John.
    Andy, Jun 14, 2006
    #7
  8. john

    Rtafas Guest

    A very good point. Have you tried using a reset? Something like:

    q <= d when clk'event and clk = '1' else '0' when rst = '1';

    I imagine that using a clock enable, must be this way.

    q <= d when clk'event and clk = '1' and clken = '1' else '0' when rst =
    '1';

    If synthesizable, it is an interesting aprouch. Have you tried such
    situations?


    Andy escreveu:

    > You do not have to have an _explicit_ process to save information:
    >
    > q <= d when rising_edge(clk); -- flip flop
    >
    > q <= d when en = '1'; -- latch
    >
    > output <= a when sel = '11' else b when sel = '00'; -- mux + latch
    >
    > That said, latches are not generally a good idea in ASICs and FPGAs.
    >
    > Andy
    >
    >
    > Rtafas wrote:
    > > Have you ever considered reading some digital systems book and/or heard
    > > about flip-flops or latches? VHDL and it's "a lot more understandable"
    > > with this knowledge. You shoud *really* do this.
    > >
    > > You must use a process to save information. Flip-flops and latches are
    > > generetade only this way. Something like:
    > >
    > > process(clk)
    > > begin
    > > if clk'event and clk = '1' then
    > > if sel_lines = "11" then
    > > out <= a;
    > > elsif sel_lines = "00" then
    > > out <= b;
    > > end if;
    > > end if;
    > > end process;
    > >
    > > What you have been reading was about assyncronous logic (gates). It
    > > won't save any value for you.
    > >
    > > Regards,
    > >
    > > Ricardo
    > >
    > > john escreveu:
    > >
    > > > Hi,
    > > >
    > > > I am trying to build a multiplexer. It has two select lines . When its
    > > > '11', it selects A when its '00' it selects B . Now, i do not want to
    > > > select anything else and maintain A or B at its output even the select
    > > > line changes to anything else like "01" or "10"... How can I do that .
    > > > I saw may examples and found that { when others => A <= ( others =>
    > > > 'X' ) }
    > > >
    > > > John.
    Rtafas, Jun 14, 2006
    #8
  9. On 14 Jun 2006 10:18:50 -0700, "john" <> wrote:

    > Have you ever considered to read writers like
    > shakespear or milton or books like Bible or Quran or intorduction to
    >ethics. If not, you should read them, before you die. because
    >engineering or sciences , did take alot of common sense from your
    >brain.


    It is entirely possible to be a good engineer who also possesses
    common-sense and some familiarity with both high culture and
    ethics. It is, however, impossible to be a good engineer
    without first finding out something about what other
    engineers have done in the past. Consequently, the advice
    you received to consult a standard digital design text was
    well-considered and highly appropriate.

    As others have pointed out, it is perfectly possible to mix
    Shakespeare and HDLs:

    architecture soliloquy of prince_of_denmark is
    signal question: bit_vector (7 downto 0);
    begin
    question <= X"2B" OR (NOT X"2B");
    end;

    Milton may be a little trickier, and of course Goedel is
    in principle impossible to express in any finite
    programming language :)
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jun 15, 2006
    #9
  10. "Rtafas" <> writes:

    > A very good point. Have you tried using a reset? Something like:
    >
    > q <= d when clk'event and clk = '1' else '0' when rst = '1';
    >
    > I imagine that using a clock enable, must be this way.
    >
    > q <= d when clk'event and clk = '1' and clken = '1' else '0' when rst =
    > '1';
    >
    > If synthesizable, it is an interesting aprouch. Have you tried such
    > situations?
    >


    I just stuck this through Synplify, and it's fine with Andy's
    original. It doesn't like yours, but it's OK with:
    q1 <= '0' when rst = '1' else d1 when rising_edge(clk);
    q2 <= '0' when rst = '1' else d2 when rising_edge(clk) and clken =
    '1';

    Anyone else care to try it on other tools? Here's the full code:

    library ieee;
    use ieee.std_logic_1164.all;

    entity ffs is
    port (
    clk : in std_logic;
    clken : in std_logic;
    rst: in std_logic;
    d,d1,d2 : in std_logic;
    q, q1,q2 : out std_logic
    );

    end entity ffs adder;
    architecture a1 of ffs adder is
    begin
    q <= d when rising_edge(clk);
    q1 <= '0' when rst = '1' else d1 when rising_edge(clk);
    q2 <= '0' when rst = '1' else d2 when rising_edge(clk) and clken = '1';
    end architecture a1;

    Cheers,
    Martin

    >
    > Andy escreveu:
    >
    > > You do not have to have an _explicit_ process to save information:
    > >
    > > q <= d when rising_edge(clk); -- flip flop
    > >
    > > q <= d when en = '1'; -- latch
    > >
    > > output <= a when sel = '11' else b when sel = '00'; -- mux + latch
    > >
    > > That said, latches are not generally a good idea in ASICs and FPGAs.
    > >
    > > Andy
    > >
    > >
    > > Rtafas wrote:
    > > > Have you ever considered reading some digital systems book and/or heard
    > > > about flip-flops or latches? VHDL and it's "a lot more understandable"
    > > > with this knowledge. You shoud *really* do this.
    > > >
    > > > You must use a process to save information. Flip-flops and latches are
    > > > generetade only this way. Something like:
    > > >
    > > > process(clk)
    > > > begin
    > > > if clk'event and clk = '1' then
    > > > if sel_lines = "11" then
    > > > out <= a;
    > > > elsif sel_lines = "00" then
    > > > out <= b;
    > > > end if;
    > > > end if;
    > > > end process;
    > > >
    > > > What you have been reading was about assyncronous logic (gates). It
    > > > won't save any value for you.
    > > >
    > > > Regards,
    > > >
    > > > Ricardo
    > > >
    > > > john escreveu:
    > > >
    > > > > Hi,
    > > > >
    > > > > I am trying to build a multiplexer. It has two select lines . When its
    > > > > '11', it selects A when its '00' it selects B . Now, i do not want to
    > > > > select anything else and maintain A or B at its output even the select
    > > > > line changes to anything else like "01" or "10"... How can I do that .
    > > > > I saw may examples and found that { when others => A <= ( others =>
    > > > > 'X' ) }
    > > > >
    > > > > John.

    >


    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.trw.com/conekt
    Martin Thompson, Jun 15, 2006
    #10
  11. john

    Ben Jones Guest

    "Jonathan Bromley" <> wrote in message
    news:...
    >
    > As others have pointed out, it is perfectly possible to mix
    > Shakespeare and HDLs:
    >
    > architecture soliloquy of prince_of_denmark is
    > signal question: bit_vector (7 downto 0);
    > begin
    > question <= X"2B" OR (NOT X"2B");
    > end;
    >
    > Milton may be a little trickier


    The top-level would be something like:

    architecture lost of paradise is

    type satan_t is (GIANT, CHERUB, CORMORANT, TOAD, SERPENT);
    signal satan : satan_t;

    begin

    process(reset, uriel, man, satan)
    begin
    if reset = '1' then
    satan <= GIANT;
    elsif uriel = '1' then
    satan <= CHERUB;
    elsif satan'descending then
    satan <= CORMORANT;
    elsif falling_edge(man) then
    satan <= TOAD;
    satan <= SERPENT after 604800000 ms;
    end if;
    end process;

    end lost;

    I think you'd need a 10-man verification team and another 50,000 lines of
    HDL to do it properly though. :)

    -Ben-
    Ben Jones, Jun 15, 2006
    #11
  12. john

    Andy Guest

    I should have noted in my previous post that these concurrent statement
    versions of registers are not the most efficient to simulate. The
    sensitivity list of the process implied by the concurrent assignment
    statement includes every signal appearing on the RHS of the statement,
    therefore including D. This does not affect the simulation results.
    For a few occurrences it would not make much difference in performance
    either, since the processes will not really do anything but wake up,
    check the clock, and go back to sleep on events on D. But this thwarts
    an important optimization in a lot of simulators: merging processes
    that share the same sensitivity list. In traditional synchronous
    processes, all of the lists consist of only the clock and maybe an
    asynchronous reset, allowing lots of processes to be merged, saving the
    setup/teardown of process invocation on all but one.

    So, while these are fine for the occasional use, where you "just need a
    flop", especially in structural code that does not have any (explicit)
    processes already, I would not make a habit of coding them this way,
    particularly on large projects.

    Andy
    Andy, Jun 15, 2006
    #12
  13. john

    john Guest

    Hi,

    Thanks guys.. I was out of town so I did not get a chance to look at
    the group. I will get back to you soon!

    John
    john, Jun 20, 2006
    #13
  14. john

    Chris Foster Guest

    "john" <> wrote in news:1150305530.457251.127790
    @y43g2000cwc.googlegroups.com:

    > Hi Rtafas,
    > Thanks for ur reply! Have you ever considered to read writers like
    > shakespear or milton or books like Bible or Quran or intorduction to
    > ethics. If not, you should read them, before you die. because
    > engineering or sciences , did take alot of common sense from your
    > brain.
    > I had a simple confusion about the mux. I apologize that I put it on
    > the group. But you do not have to answer it if you think its too simple
    > for u. why did u bother to answer it. let it answer by other people.
    > Regards
    > John
    >
    >


    WOW After helping him, he gives you a rash of shit. What an ass

    --
    Posted via a free Usenet account from http://www.teranews.com
    Chris Foster, Jun 21, 2006
    #14
  15. john

    john Guest

    Hello,
    It is, however, impossible to be a good engineer
    without first finding out something about what other
    engineers have done in the past.

    I agree with you. The same rules applies to writers too. I suggest you
    that when you try to experiemnt with ethics, you should lookup the past
    works of shakespear, milton or jesus. And do not mock them by
    arrogantly mixing them with your living making tool VHDL. God knows why
    DOD invented VHDL? What were they intentions to build it? But history
    will tell you that the writers I mentioned above did have true
    intentions about the people and their true prosperity.
    I think you should think about reading those books before it gets too
    late. you can not define those works with VHDL or believe me you or
    yourself do not want to be defined by VHDL too
    Please consider my highly appropiate advice!
    Regards,
    John
    john, Jun 22, 2006
    #15
  16. On 22 Jun 2006 09:06:29 -0700, "john" <> wrote:

    [...]
    >I think you should think about reading those books before it gets too
    >late.


    I think you should reconsider your arrogant and unjustified
    assumptions about my reading habits.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jun 22, 2006
    #16
  17. On 14 Jun 2006 08:17:28 -0700, "john" <> wrote:

    >I am trying to build a multiplexer. It has two select lines . When its
    >'11', it selects A when its '00' it selects B . Now, i do not want to
    >select anything else and maintain A or B at its output even the select
    >line changes to anything else like "01" or "10"


    This isn't really a multiplexer; it's similar to a "Muller C-element"
    used in self-timed logic design. It's quite a challenge to build
    self-timed logic primitives in an FPGA, because the
    optimisations generally are designed to work well on
    synchronous rather than asynchronous circuits. A simulation
    model is easy enough to create:

    signal A, B, Y: ...;
    signal S: std_logic_Vector (1 downto 0);
    ....
    process (A, B, S)
    begin
    case S is
    when "00" =>
    Y <= B;
    when "11" =>
    Y <= A;
    when "10" | "01" =>
    null; -- no change
    when others =>
    report "Selector contains meta-values"
    severity error;
    end case;
    end process;

    Synthesis will build from this a latch that is frozen when the XOR of
    S(0) and S(1) is '1', and a multiplexer selected by either bit of
    S (obviously it doesn't matter which). It is not at all obvious that
    synthesis and place-and-route will preserve a hazard-free
    implementation all the way through to the FPGA implementation.
    You may need to develop a hazard-free netlist of this element
    and then set it up as a relatively-placed macro, making sure
    that it has "don't optimize" attributes on it whenever you
    use it. This is definitely not my area of expertise, but
    I hope some of the comments above may point you in
    the right direction.

    For a readable introduction, with a few useful references, try
    http://www.sun.com/processors/throughput/SciAm_Reprint.pdf
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jun 22, 2006
    #17
  18. john wrote:

    > Please consider my highly appropiate advice!


    It is neither appropriate nor on-topic in this newsgroup.

    -- Mike Treseler
    Mike Treseler, Jun 22, 2006
    #18
  19. john

    john Guest

    Hi,
    Thanks Mike.

    Regards
    John
    john, Jun 22, 2006
    #19
  20. john

    john Guest

    Hi,
    I think you should reconsider your arrogant and unjustified
    > assumptions about my reading habits.


    I am not concern about your reading habits my friend. I am just
    concerned about what you do after reading them.

    Regards
    John
    john, Jun 22, 2006
    #20
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