MULTIPLIER Inpots

Discussion in 'VHDL' started by Bar Nash, Oct 8, 2008.

  1. Bar Nash

    Bar Nash Guest

    Hi all

    When a multipler is designed like those used in FIRS will the nature of the
    multiplicands influence the structure of it ?

    I mean in case those are both fractional numbers <1 and in case both are
    whole numbers .

    I hope I described clear enough the problem .

    Thanks in advance
    EC
     
    Bar Nash, Oct 8, 2008
    #1
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  2. Bar Nash

    KJ Guest

    On Oct 8, 8:34 am, "Bar Nash" <> wrote:
    > Hi all
    >
    > When a multipler is designed like those used in FIRS will the nature of the
    > multiplicands influence the structure of  it ?
    >
    > I mean in case those are both fractional numbers <1 and in case both are
    > whole numbers .
    >


    It shouldn't. I'm assuming your question is targetted towards
    multipliers meant to be synthesized, that being the case the first
    step would be to define how you plan to represent numbers in general.
    Depending on the particular needs of your FIR filters the numbers will
    likely be either fixed point or floating point. Fixed point
    representation will consume less logic than floating point but either
    can be synthesized.

    If you use the relatively newly standardized fixed or floating point
    packages as the basis for representing 'numbers' then the answer to
    your question is 'no, the structure of the multiplier will not be
    influenced by the nature of the multiplicands'.

    For more info on these packages, root around at vhdl.org. The link
    below takes you to the user's guide for the fixed point package.

    http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf

    Kevin Jennings
     
    KJ, Oct 8, 2008
    #2
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  3. Bar Nash

    Bar Nash Guest

    Thanks
    EC

    "KJ" <> ???
    ??????:...
    On Oct 8, 8:34 am, "Bar Nash" <> wrote:
    > Hi all
    >
    > When a multipler is designed like those used in FIRS will the nature of
    > the
    > multiplicands influence the structure of it ?
    >
    > I mean in case those are both fractional numbers <1 and in case both are
    > whole numbers .
    >


    It shouldn't. I'm assuming your question is targetted towards
    multipliers meant to be synthesized, that being the case the first
    step would be to define how you plan to represent numbers in general.
    Depending on the particular needs of your FIR filters the numbers will
    likely be either fixed point or floating point. Fixed point
    representation will consume less logic than floating point but either
    can be synthesized.

    If you use the relatively newly standardized fixed or floating point
    packages as the basis for representing 'numbers' then the answer to
    your question is 'no, the structure of the multiplier will not be
    influenced by the nature of the multiplicands'.

    For more info on these packages, root around at vhdl.org. The link
    below takes you to the user's guide for the fixed point package.

    http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf

    Kevin Jennings
     
    Bar Nash, Oct 10, 2008
    #3
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