multiplier with one fixed value other user defined

[xiibweb]

Hi,,
I am interested to write a code in VHDL where one input is user defined
and the
other input is fixed to some value....

for example

0X2=0
1X2=2
2X2=4
3X2=6

here two in fixed (which I want to define as fixed). and 0 , 1, 2 , 3
user defined.

This code is generated using Xilinx webpack...

================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multo is
Port ( p1 : in std_logic_vector(1 downto 0);
w1 : in std_logic_vector(1 downto 0);
ou : out std_logic_vector(3 downto 0));
end multo;

architecture Behavioral of multo is

begin

ou <= w1 * p1;

end Behavioral;

================================================================

the code works fine.. but in a final result I hv to make a schmatic
symbol for the code.. and I want to keep the fixed input hidden. So the
user just can change the other input and see the results... but with
existing code user cn c both inputs and requires to define both.

anybody with an answer... help me out...

thanks

John

 

[Mohammed A khader]

Hi John,

To have a fixed input it must be a constant (not a input port). So you
have to change your code to
================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multo is
Port ( w1 : in std_logic_vector(1 downto 0);

ou : out std_logic_vector(3 downto 0));
end multo;

architecture Behavioral of multo is

constant p1 : std_logic_vector(1 downto 0):= "10";

begin

ou <= w1 * p1;

end Behavioral;

================================================================

There are other things to correct in code. You have included the
package for unsigned and arithmetic but have not used it. When you do
some arithmetic opearation then it is good to define operators by
either unsigned or signed But dont use std_logic_vector. I assume you
want to do unsgined multiplication , so use unsigned type rather then
std_logic_vector.

Hence your declarations must be

w1 : in unsigned(1 downto 0); .....

-- Mohammed A Khader.

 

[xiibweb]

well the problem is not solved......... i cannot hide the input
still... or keep it defined...
thanks.

 

[xiibweb]

Well thanks very much for the reply...
i am getting following errors when i try to do compilation...

ERROR:HDLParsers:800 - "C:/Projects/AndNN/multhree.vhd" Line 14. Type
of p1 is incompatible with type of 10 .
ERROR:HDLParsers:808 - "C:/Projects/AndNN/multhree.vhd" Line 17. * can
not have such operands in this context

and i hv no idea how figure these out....

thanks again

 

[xiibweb]

THANKS A LOOOOOOOOOOOOOOOOOOOOT........... NOW THE CODE IS WORKING
FINEEEEEEEEEEEEEEE

THANKS AGAIN

John

 

[info_]

Hi John,

To have a fixed input it must be a constant (not a input port). So you
have to change your code to
================================================================


constant p1 : std_logic_vector(1 downto 0):= "10";




There are other things to correct in code. You have included the
package for unsigned and arithmetic but have not used it.

Yes he did !
that's what std_logic_unsigned is about :
it treats std_logic_vectors as unsigned.

Hence your declarations must be

w1 : in unsigned(1 downto 0); .....

-- Mohammed A Khader.

Not necessary. see above.

But I think everyone should give up synopsys arith packages and
switch to numeric_std instead.

Bert Cuzeau

 

[Mohammed A khader]

Mohammed said ....
Bert Said....

that's what std_logic_unsigned is about :
it treats std_logic_vectors as unsigned.

Sorry I wrote unsigned as well as arithmetic . * operator for
std_lgoic_vector is defined in unsigned .So no need of arithmetic
package since it is not used.

But I think everyone should give up synopsys arith packages and
switch to numeric_std instead.

Yes I agree with it.