Multiplier

[Quinnie]

I need VHDL code for Modified Booth's multiplier and Add/Shift
multiplier. They have to be structural design (not behavorial)...Any
help would be greatly appreciated. Thnx!

 

[Ingmar Seifert]

I need VHDL code for Modified Booth's multiplier and Add/Shift
multiplier. They have to be structural design (not behavorial)...Any
help would be greatly appreciated. Thnx!

Hello,

at first: Please use your realname for further postings. Otherwise some
people won't answer your questions.
The second thing is that I don't think that anyone would give you a
"ready to go" VHDL code.
I recently had to write a serial multiplier. The drawings on the
following page gave me some help.
http://www.csee.umbc.edu/help/VHDL/samples/samples.shtml
It shouldn't be that much work to desribe the shiftregisters, the adder
and the and gates in a structural way.


Good luck in describing the units.
Ingmar Seifert

 

[Ralf Hildebrandt]

I need VHDL code for Modified Booth's multiplier

Signed / Unsigned? Both? ;-)

The Booth-Encoder ist is combinational logic. If you understand the
mathematical principle, it is very easy to implement.

The generation of the partial products (PPG) depends on whether signed /
unsigned multipication or both is needed. There are some tricks for sign
extension, too.

The partial product reduction (PPR) is "free" to implement. CSA and
Wallace-Tree are the most common.

The final Carry-Propagate-Adder (CPA) is also "free". CLA is the most
common.

and Add/Shift
multiplier. They have to be structural design (not behavorial)...Any
help would be greatly appreciated. Thnx!

Uhmm .. this is a VHDL-newsgroup, not a market for IP cores. ;-)


I recommended the following links:
Booth encoded array multipliers:
http://arith.cs.ucla.edu/dissertations/dissertation_huang03.pdf
fast CPA:
http://twins.ee.nctu.edu.tw/~chsung/dissertation_ts2.pdf

Ralf

 

[Quinnie]

Hi,
Thank you all for replying. I know the algorithm well and actually
got the booth and shift/add multiplier to work but I use process only
(behavorial) while I supposed to use to adder to add instead....I'm
very confused because process doesn't allow port map inside it. Any
thoughts? Thanks a lot.

Btw, I only need to implement unsigned booth and unsigned multipliers.
Thnx

Quynh Pham (there goes my real name, what is the point if anyone could
just put up any name ?

 

[Ralf Hildebrandt]

Quinnie wrote:

Thank you all for replying. I know the algorithm well and actually
got the booth and shift/add multiplier to work but I use process only
(behavorial)

It does not depend on VHDL processes, if you are writing behavioral
descriptions oder synthesizable models. A process is nothing more than a
"box" for the language. What you put into the box depends on you.

while I supposed to use to adder to add instead....

What adder?

sum <= std_ulogic_vector( unsigned(input_A) + unsigned(input_B) );

is a synthesizable adder.

I'm
very confused because process doesn't allow port map inside it.

Why do you want to do this? I can't see any reason.



Do you think like writing a software with C, Pascal or whatever? - Get
this out of your mind. VHDL is a tool, that helps you modelling
hardware. Hardware has to be described / modelled and not programmed!



Make a 1st component, that has the 2. operand as input and the Booth
encoded version as output.

Make a 2nd component, that uses the 1. operand and the Booth encoded 2.
operand. This component has to produce the multiplier arrary (partial
product generation). The outputs are all the vectors in the multiplier
array.

Make a 3rd component, that takes all the vectors from the multiplier
array and sums them up. (Wallace-Tree, CSA or whatever). The result are
eigther 2 Vectors (Carrys und Sums if you have chosen WT oor CSA) or the
final sum (if you do something special).

Make a last component (if you have chosen WT or CSA), that sums up the 2
results from the 3rd component. This component is the
craay-propageate-adder.

As you can see: All component are pure combinational logic (if you did a
parallel multiplier).


Ralf