multiplier

Discussion in 'VHDL' started by Scofield, Aug 19, 2006.

  1. Scofield

    Scofield

    Joined:
    Aug 19, 2006
    Messages:
    1
    Hello.
    I need to write a multiplier in VHDL which multiplies two 32 bit registers,
    assuming that the result is never bigger than 32 bits.

    we used the following code:

    ENTITY mult_rg IS
    PORT (
    d_in1: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    d_in2: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    d_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
    END mult_rg;

    ARCHITECTURE rtl OF mult_rg IS
    SIGNAL a_int, b_int: SIGNED (31 downto 0);
    SIGNAL pdt_int: SIGNED (31 downto 0);

    BEGIN
    a_int <= SIGNED (d_in1);
    b_int <= SIGNED (d_in2);
    pdt_int <= a_int * b_int;
    d_out <= STD_LOGIC_VECTOR(pdt_int);
    END rtl;

    but I got the following error messege:

    Length of expected is 32; length of actual is 64.

    What should I do?
    thanx.
     
    Scofield, Aug 19, 2006
    #1
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  2. Scofield

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
    7
    when you multiply two 32 bit numbers, the resultant is always 2 * 32 bits long at max 64 bits long ...

    u can test this out by doing (2^32 - 1)(2^32-1) = (2^64 - 2^33 - 2)

    i multiplied the two largest 32 bit numbers possible..and as u can see, the resultant is a 64 bit number

    hence, change your d_out to (63 downto 0)...that'll fix it
     
    Jerrie85, Aug 19, 2006
    #2
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