Hello.
I need to write a multiplier in VHDL which multiplies two 32 bit registers,
assuming that the result is never bigger than 32 bits.
we used the following code:
but I got the following error messege:
Length of expected is 32; length of actual is 64.
What should I do?
thanx.
I need to write a multiplier in VHDL which multiplies two 32 bit registers,
assuming that the result is never bigger than 32 bits.
we used the following code:
ENTITY mult_rg IS
PORT (
d_in1: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
d_in2: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
d_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END mult_rg;
ARCHITECTURE rtl OF mult_rg IS
SIGNAL a_int, b_int: SIGNED (31 downto 0);
SIGNAL pdt_int: SIGNED (31 downto 0);
BEGIN
a_int <= SIGNED (d_in1);
b_int <= SIGNED (d_in2);
pdt_int <= a_int * b_int;
d_out <= STD_LOGIC_VECTOR(pdt_int);
END rtl;
PORT (
d_in1: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
d_in2: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
d_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END mult_rg;
ARCHITECTURE rtl OF mult_rg IS
SIGNAL a_int, b_int: SIGNED (31 downto 0);
SIGNAL pdt_int: SIGNED (31 downto 0);
BEGIN
a_int <= SIGNED (d_in1);
b_int <= SIGNED (d_in2);
pdt_int <= a_int * b_int;
d_out <= STD_LOGIC_VECTOR(pdt_int);
END rtl;
but I got the following error messege:
Length of expected is 32; length of actual is 64.
What should I do?
thanx.