multiplier

Discussion in 'VHDL' started by power_hf2005, Sep 23, 2009.

  1. power_hf2005

    power_hf2005

    Joined:
    Sep 23, 2009
    Messages:
    6
    hi all,
    I design a multiplier but I have a mistake that I can not understand why. It always reports this sentence:"Can't determine definition of operator ""sll""--found posible definition".I think because I use "sll" keyword in a wrong way but I don't know how to correct.Help me plz!
    Here is my code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use ieee.numeric_std.all;
    --------------------------
    entity nhan is
    port(a: in std_logic_vector(3 downto 0);
    b: in std_logic_vector(3 downto 0);
    kq: out std_logic_vector( 7 downto 0));
    end nhan;
    --------------------------
    architecture nhan of nhan is
    type mang is array( 0 to 3) of std_logic_vector(7 downto 0);
    begin
    process(a,b)
    variable x: mang;
    variable t: std_logic_vector(7 downto 0);
    begin
    for j in 0 to 3 loop
    if b(j)='1' then
    x(j):=("0000"& a) sll j;
    else
    x(j):=(others =>'0');
    end if;
    t:=t+x(j);
    end loop;
    kq<=t;
    end process;
    end nhan;
    power_hf2005, Sep 23, 2009
    #1
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  2. power_hf2005

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    Try this

    x(j):= std_logic_vector( unsigned("0000"& a) sll j );


    You need to check the data types that the functions require.
    StuartHobday, Sep 24, 2009
    #2
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  3. power_hf2005

    power_hf2005

    Joined:
    Sep 23, 2009
    Messages:
    6
    Thanks, but It's not better.:(
    power_hf2005, Sep 24, 2009
    #3
  4. power_hf2005

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    The following code compiles OK in Lattice tools but unfortunately I don't have the Xilinx tools on this laptop, will check when back in the office. See if this helps!!

    I have added brief comments to the code detailing specific changes.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.all;

    -- !!! DON'T USE THESE LIBRARIES - NON STANDARD IEEE LIBS !!!
    --use IEEE.STD_LOGIC_ARITH.ALL;
    --use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity nhan is
    port( a: in std_logic_vector(3 downto 0);
    b: in std_logic_vector(3 downto 0);
    kq: out std_logic_vector(7 downto 0)
    );
    end nhan;


    architecture Behavioural of nhan is

    type mang is array( 0 to 3) of std_logic_vector(7 downto 0);

    begin

    process(a,b)
    variable x: mang;
    -- changed type from std_logic_vector to integer as std_logic_vector increments
    -- are not possible with the above ieee library standards...
    variable t: integer range 0 to 255;
    variable y : std_logic_vector(7 downto 0);
    begin
    for j in 0 to 3 loop
    if b(j)='1' then
    -- concatenation on std_logic_vectors
    y:= "0000" & a;

    -- sll takes unsigned arguments, hence convert y to unsigned type.
    -- x storage is in std_logic_vector, hence convert std_logic_vector.
    x(j) := std_logic_vector(unsigned(y) sll j);
    else
    x(j):= (others =>'0');
    end if;

    -- Integer counter, convert std_logic_vector to natural(integer) type..
    t := t + to_integer( unsigned( x(j) ) );
    end loop;
    -- convert integer counter 't' to std_logic_vector
    kq<= std_logic_vector( to_unsigned(t, 8));
    end process;

    end;
    StuartHobday, Sep 26, 2009
    #4
  5. power_hf2005

    power_hf2005

    Joined:
    Sep 23, 2009
    Messages:
    6
    oh my god!!! I'm really happy and...I can't express my emotion. Thank you very muchhhhhhhhhhhhhhhhhhhhhh!!!!.
    StuartHobday, you are very pro. I have just study VHDL for 2 weeks so very noob.
    I'm from Vietnam and you?
    power_hf2005, Sep 29, 2009
    #5
  6. power_hf2005

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    Your welcome....

    Located in Dorset, England. Have been working with FPGA's for over ten years now.
    StuartHobday, Sep 29, 2009
    #6
  7. power_hf2005

    canito

    Joined:
    Oct 9, 2009
    Messages:
    1
    reververation-eco

    can somebody helme, I have to produce a revervaration or eco to a digital voice input (USB port) in a PC and then send it to te audio output.

    cankĀ“s
    canito, Oct 9, 2009
    #7
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