Multiplt clock synchronization problem

Discussion in 'VHDL' started by Francis, Apr 27, 2004.

  1. Francis

    Francis Guest

    hi there,
    im experiencing a multiplt clock synchronization problem while
    synthesizing my vhdl code. could any one let me know what does that
    mean.
    thanks
     
    Francis, Apr 27, 2004
    #1
    1. Advertising

  2. Francis

    Ronald Hecht Guest

    Have a look at

    http://www.sunburst-design.com/papers/

    Ronald

    Francis wrote:
    > hi there,
    > im experiencing a multiplt clock synchronization problem while
    > synthesizing my vhdl code. could any one let me know what does that
    > mean.
    > thanks
     
    Ronald Hecht, Apr 27, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,393
    louis lin
    Oct 28, 2003
  2. Replies:
    4
    Views:
    761
    Peter Alfke
    Apr 27, 2006
  3. Replies:
    5
    Views:
    2,265
    Ricardo
    Jun 23, 2006
  4. john
    Replies:
    10
    Views:
    1,237
    JohnDuq
    Apr 21, 2009
  5. SLH
    Replies:
    6
    Views:
    187
    Bob Barrows [MVP]
    Oct 5, 2006
Loading...

Share This Page