Multuple output drivers

[Chris Taylor]

I understand the basics behind multiple driver signal resolution using
std_logic_vector's within a single process.


e.g.
if Read = '0' and Enable1 = '0' then
DataBus <= RegisterA;
elsif Read = '0' and Enable2 = '0' then
DataBus <= RegisterB;
else
DataBus <= (others => 'Z');
end if;


However when you create a design with multiple modules consisting of
different registers which can be read by an external device via the
data bus how to you go about resolving the data bus status as the
synthesis tool will just throw up an error of multiple drivers for
data bus.

The only way I have found around this problem is to create a separate
bus (resolved in its own module process) coming out of each module.
These separate buses are all passed back to a common data bus handler
module which decides which bus to connect out to the data bus if any
otherwise it tri-states the data bus.

Is there an easier way of performing this type of signal resolution.

Thanks in advance for any help.

 

[Mike Treseler]

Chris Taylor wrote

The only way I have found around this problem is to create a separate
bus (resolved in its own module process) coming out of each module.
These separate buses are all passed back to a common data bus handler
module which decides which bus to connect out to the data bus if any
otherwise it tri-states the data bus.

Is there an easier way of performing this type of signal resolution.

Sounds like you're on the right track.

Note that any process can read the
external bus without contention.

Since you only need to arbitrate bus drivers,
consider separate input and output signals
everywhere except where the top level
bus handler actually drives the bidirectional pins.

Synthesis can move tristate buffers to the surface for you,
but this makes a mess of the design signal names.

-- Mike Treseler