Mutiple drivers on the same line

Discussion in 'VHDL' started by Christopher Bunk, Jul 8, 2003.

  1. If I have multiple drivers on a STD_LOGIC signal(either a port or a local
    signal), and all the drivers write a Z to it, what value will the module
    reading the signal see? I have control lines going into one of my modules
    and when nobody is using it they all write Z's to it. I want to make sure
    that when nobody is using it that it doesn't do anything bad. Is there a
    way to set a default value to it?

    Thanks
    Christopher Bunk, Jul 8, 2003
    #1
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  2. Even when synthesized? So, then I could compare the signal to Z when it's
    synthesized?


    "Mike" <> wrote in message
    news:bed6ip$3v6$...
    > If multiple drivers write "Z" at the same time, you should still get "Z".
    >
    > "Christopher Bunk" <> wrote in message
    > news:1OoOa.25011$...
    > > If I have multiple drivers on a STD_LOGIC signal(either a port or a

    local
    > > signal), and all the drivers write a Z to it, what value will the module
    > > reading the signal see? I have control lines going into one of my

    modules
    > > and when nobody is using it they all write Z's to it. I want to make

    sure
    > > that when nobody is using it that it doesn't do anything bad. Is there

    a
    > > way to set a default value to it?
    > >
    > > Thanks
    > >
    > >

    >
    >
    Christopher Bunk, Jul 8, 2003
    #2
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  3. Christopher Bunk wrote:
    >
    > Even when synthesized? So, then I could compare the signal to Z when it's
    > synthesized?
    >
    > "Mike" <> wrote in message
    > news:bed6ip$3v6$...
    > > If multiple drivers write "Z" at the same time, you should still get "Z".


    Yes, even when synthesized, IFF the synthesizer, part, and synthesis
    library you're using support tri-state drivers at the level you're
    trying to infer the tri-state drivers.

    No, you can't compare against 'Z'. Try to think about how would you
    create hardware to do that. The synthesizer can't magically create
    things that aren't physically possible.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jul 8, 2003
    #3
  4. Christopher Bunk

    Jon Guest

    Hi Christopher,
    STD_LOGIC uses a resolution table to figure out what value to put
    out on the bus when there are multiple drivers. In general unless you
    code the VHDL correctly to infer tri-state drivers you should get
    errors in synthesis that there is a net driven by more than one
    source. I assume that you have at least synthesized the vhdl code
    successfully. In general after synthesis if you have multiple drivers
    and each driver is in the high-impedance state (i.e. driving a Z in
    vhdl) then without a holder circuit or a default driver then the
    signal will float and go to an indeterminate state. Now the part that
    does not match reality. Depending on what post synthesis models you
    are using it is possible in the simulation to see a 'Z' on the output
    if all drivers are driving a 'Z', but that is only in simulation
    dependant on the models.

    Jon



    "Christopher Bunk" <> wrote in message news:<REpOa.25050$>...
    > Even when synthesized? So, then I could compare the signal to Z when it's
    > synthesized?
    >
    >
    > "Mike" <> wrote in message
    > news:bed6ip$3v6$...
    > > If multiple drivers write "Z" at the same time, you should still get "Z".
    > >
    > > "Christopher Bunk" <> wrote in message
    > > news:1OoOa.25011$...
    > > > If I have multiple drivers on a STD_LOGIC signal(either a port or a

    > local
    > > > signal), and all the drivers write a Z to it, what value will the module
    > > > reading the signal see? I have control lines going into one of my

    > modules
    > > > and when nobody is using it they all write Z's to it. I want to make

    > sure
    > > > that when nobody is using it that it doesn't do anything bad. Is there

    > a
    > > > way to set a default value to it?
    > > >
    > > > Thanks
    > > >
    > > >

    > >
    > >
    Jon, Jul 8, 2003
    #4
  5. Christopher Bunk

    Mario Trams Guest

    Christopher Bunk wrote:

    > If I have multiple drivers on a STD_LOGIC signal(either a port or a local
    > signal), and all the drivers write a Z to it, what value will the module
    > reading the signal see?


    You already received valuable answers here.

    > I have control lines going into one of my modules
    > and when nobody is using it they all write Z's to it. I want to make sure
    > that when nobody is using it that it doesn't do anything bad. Is there a
    > way to set a default value to it?


    For simulation purpuses you can assign 'H' or 'L' in order to provide
    a virtual pullup or pulldown resistor. This will give you a valid
    reading of the signal.

    Say:

    bla <= 'H'; -- pullup

    bla <= blubber when a1='1' else 'Z'; -- driver1
    bla <= blabber when a2='1' else 'Z'; -- driver2

    For synthesis, however, this will be ignored very likely. Except for
    the case that the target hardware provides something like pullup
    or pulldown resistors.

    Regards,
    Mario
    Mario Trams, Jul 8, 2003
    #5
  6. Hmm...maybe I should have posted some code. Basically I want to know when I
    synthesize this code:

    process(command, currentState)
    begin
    case currentState is
    when IDLE =>
    -- Do nothing
    if(command = DONOTHING) then
    nextState <= IDLE;
    -- the command is a read
    elsif(command(4) = '1') then
    nextState <= R_INITREAD1;
    -- the command is a set pixel
    elsif(command = SETPIXEL) then
    nextState <= W_INITREAD;
    -- the command is a write that doesn't need a read
    elsif(command(4) = '0') then
    nextState <= W_SETUP1;
    else
    nextState <= IDLE;
    end if;
    ..........

    where command is an input port to the entity defined as UNSIGNED(4 downto
    0). If all the drivers are writing ZZZZZ to the command line and the
    current state is IDLE, what will the nextState signal be?



    "Christopher Bunk" <> wrote in message
    news:1OoOa.25011$...
    > If I have multiple drivers on a STD_LOGIC signal(either a port or a local
    > signal), and all the drivers write a Z to it, what value will the module
    > reading the signal see? I have control lines going into one of my modules
    > and when nobody is using it they all write Z's to it. I want to make sure
    > that when nobody is using it that it doesn't do anything bad. Is there a
    > way to set a default value to it?
    >
    > Thanks
    >
    >
    Christopher Bunk, Jul 8, 2003
    #6
  7. Christopher Bunk wrote:
    > Hmm...maybe I should have posted some code. Basically I want to know when I
    > synthesize this code:
    >
    > process(command, currentState)
    > begin
    > case currentState is
    > when IDLE =>
    > -- Do nothing
    > if(command = DONOTHING) then
    > nextState <= IDLE;
    > -- the command is a read
    > elsif(command(4) = '1') then
    > nextState <= R_INITREAD1;
    > -- the command is a set pixel
    > elsif(command = SETPIXEL) then
    > nextState <= W_INITREAD;
    > -- the command is a write that doesn't need a read
    > elsif(command(4) = '0') then
    > nextState <= W_SETUP1;
    > else
    > nextState <= IDLE;
    > end if;
    > .........
    >
    > where command is an input port to the entity defined as UNSIGNED(4 downto
    > 0). If all the drivers are writing ZZZZZ to the command line and the
    > current state is IDLE, what will the nextState signal be?



    I don't think you really want command to be a bi-directional bus.

    Make command an internal signal driven from a single process
    and read by all interested processes. No 'Z's required.

    -- Mike Treseler
    Mike Treseler, Jul 8, 2003
    #7
  8. On Tue, 08 Jul 2003 16:57:29 GMT, "Christopher Bunk"
    <> wrote:

    >Hmm...maybe I should have posted some code. Basically I want to know when I
    >synthesize this code:
    >
    > process(command, currentState)
    > begin
    > case currentState is
    > when IDLE =>
    > -- Do nothing
    > if(command = DONOTHING) then
    > nextState <= IDLE;
    > -- the command is a read
    > elsif(command(4) = '1') then
    > nextState <= R_INITREAD1;
    > -- the command is a set pixel
    > elsif(command = SETPIXEL) then
    > nextState <= W_INITREAD;
    > -- the command is a write that doesn't need a read
    > elsif(command(4) = '0') then
    > nextState <= W_SETUP1;
    > else
    > nextState <= IDLE;
    > end if;
    >.........
    >
    >where command is an input port to the entity defined as UNSIGNED(4 downto
    >0). If all the drivers are writing ZZZZZ to the command line and the
    >current state is IDLE, what will the nextState signal be?


    In simulation, it will fall out the bottom of your if - else chain to
    the last else, and nextstate will get the value IDLE.

    In synthesis, it will vary depending on how tristates are modelled in
    the hardware.

    - If the hardware has true tristates, then ZZZZ may be decoded as
    garbage, and your state machine could do anything (including entering
    illegal states or locking up if you haven't been careful enough to
    avoid lock up states).

    - If your hardware has "keepers" on the tristate lines, it may retain
    the last non-Z value of the command signal.

    - If your hardware has weak "pullups" (or pulldowns) on the tristate
    lines, it may slowly float through some illegal values (crashing your
    state machine) before it settles at all ones or all zeros.

    - If your hardware has tristate emulation (e.g. some FPGAs) then the
    tristate value may turn into a command of all zeros or all ones.


    Note: in none of these cases does the hardware match the simulation
    behaviour.


    Summary: you really want to avoid testing a value for Z in your code.


    I recommend adding an extra bit to indicate when command is valid.
    Use this valid bit in your state machine to force the state to IDLE.
    (The valid bit will be the logical or of all the enable signals for
    the various drivers of the command signal.)
    This will ensure that (1) the hardware works, (2) the hardware and
    simulation will behave the same way.

    Regards,
    Allan.

    >
    >
    >"Christopher Bunk" <> wrote in message
    >news:1OoOa.25011$...
    >> If I have multiple drivers on a STD_LOGIC signal(either a port or a local
    >> signal), and all the drivers write a Z to it, what value will the module
    >> reading the signal see? I have control lines going into one of my modules
    >> and when nobody is using it they all write Z's to it. I want to make sure
    >> that when nobody is using it that it doesn't do anything bad. Is there a
    >> way to set a default value to it?
    >>
    >> Thanks
    >>
    >>

    >
    Allan Herriman, Jul 8, 2003
    #8
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