mux code

[Ralf Hildebrandt]

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

"sel" is not in sensitivity list, therefore in simulation nothing will
happen, if no input, but sel changes.

What you have done is modelling 8 Latches (out_1 to out_8). Let me
describe, what I mean with the example out_1: out_1 is driven with in_1,
when sel='1'. If sel='0' nothing will happen to out_1. This means, out_1
holds its old value. This is a "level sensitive register" aka Latch.

The following code describes 4 two-to-one muxes (out_1 to out_4):

process (sel, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_1 <= in_5;
out_2 <= in_6;
out_3 <= in_7;
out_4 <= in_8;
end if;
end process;


Ralf

 

[rajan]

Hi,

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

I would appreciate your help.

Thank you.

rajan

 

[rajan]

Hi Ralf,

Thank you for your great help. Is there a better way to write this so that
it synthesizes well (or synthesizes without latches).

 

[anupam]

Hi Rajan,
Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'

 

[Ralf Hildebrandt]

Thank you for your great help. Is there a better way to write this so that
it synthesizes well (or synthesizes without latches).

Then let us know, what do you really want! Which input signals (plural -
not singular!) should be muxed to which output (singular, not plural)?

(You did not describe any mux so I can only guess, what your intention was.)

In all cases - the solution I've posted, should be a good template to
adopt it to you own requirements:

f'up comp.lang.vhdl

Ralf

 

[valentin tihomirov]

Pl add the "sel" in sensitivity list and assign the value to
out_5,....,out_8 at sel = '1' and value to out_1,....,out_4 at sel = '0'

Is'nt it what he is doing now? It was mentioned that latches will be
incured.

 

[valentin tihomirov]

process (SEL, I0, I1)
begin
case SEL is
when '0' => O <= I0;
when '1' => O <= I1;
when others => O <= 'X'; -- optional line
end case;
end process;

http://www.google.com/search?sourceid=navclient&ie=UTF-8&q=mux2+vhdl

 

[Klaus Falser]

Hi,

I want to ask you if the following code written is correct:

process (in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8)
begin
if (sel = '1') then
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
out_4 <= in_4;
else
out_5 <= in_5;
out_6 <= in_6;
out_7 <= in_7;
out_8 <= in_8;
end if;
end process;

I would appreciate your help.

Thank you.

rajan

IMHO the simplest way to write a 2-way multiplexer for switching
between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

The second recommandation for you is to learn to use
vectors.
It is much more readable and less error prone if you
write

out(4 downto 1) <= input(4 downto 1);

instead of writing 4 single assignments.

Best regards

 

[valentin tihomirov]

IMHO the simplest way to write a 2-way multiplexer for switching

between 2 signals is :

MuxedOut <= SignalA when sel= '1' else SignalB;

This is short and there is no need to worry about sensitivity
lists.

Will these internal muxes be supported in VHDLXX

MuxedOut <= A when S1 else (B when S2 else C);


???

 

[Thomas Stanka]

Will these internal muxes be supported in VHDLXX

MuxedOut <= A when S1 else (B when S2 else C);

Yes, at least if you remove the brackets.

You have two conccurent muxes with some different behavior. Both could
be used to build simple 2-to-1 Muxes.

1)
WITH Mux_selector SELECT
output<=A WHEN '0',
B WHEN '1';
2)
output<=A WHEN Cond1 ELSE
B WHEN Cond2 ELSE
C;

bye Thomas