MUX with generate statement

Discussion in 'VHDL' started by RADNOR, Jul 20, 2011.

  1. RADNOR

    RADNOR

    Joined:
    Jul 20, 2011
    Messages:
    4
    Hello,

    lets say i have some signal select_signal, and that is one-hot type of a signal, so at any time only one of its bits is 1, others are 0.

    The number of bits in that signal depends on the GENERIC statement describing the top entity.

    Now i want to create a MUX which will use that select_signal as a control signal, and of course which will also depend on the number of bits defined in top level entity.

    now what would be the most compact, nice and efficient method to do that with generate statement?

    for example its possible to do in VHDL things like that:
    Code:
    my_signal <= (127 => '1', others=>'0');
    as you see there i am assigning bit #127 value 1, others are zeros.

    Now in my problem it has to be vice versa, i must inside the generate statement create such a mux which compares specific bit and makes sure that others are zero..

    any thoughts?

    thank you
    RADNOR, Jul 20, 2011
    #1
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  2. RADNOR

    flymolo

    Joined:
    Jun 2, 2011
    Messages:
    10
    Hmm,I think the efficiency of one-hot comes from the fact that You don't need to compare if other bits are zero. Assuming the mux input is an array type and array size matches select_signal size (well not exactly size but index range)
    Code:
    ...
    mux_out <= (others => '0') -- default
    for i in select_signal'range loop
      if select_signal(i) = '1' then
        mux_out <= mux_in(i);
      end if;
    end loop;
    ...
    
    Which is similar to RAM/ROM description, i don't know if there is any penalty using this vs regular case statement (probally there is as it is priority based), however sometimes I am using this style and i never had a problem with it. What you may didn't know is you can declare entity with unconstrained array ports and use signal attributes to extract range, size etc. instead using generic.
    On the second thought it might be more convenient to use generic to unify selector length and mux input array length. Also you said you want to check if one bit is '1' and others are '0', but what if they are not?
    Last edited: Jul 20, 2011
    flymolo, Jul 20, 2011
    #2
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  3. RADNOR

    RADNOR

    Joined:
    Jul 20, 2011
    Messages:
    4
    well thanks for advice, but as you yourself noticed its not gona be that efficient because of its nested comparison nature.

    well it actually turns out that i do not need to see if others are zero, once i noticed that any bit of the select_signal is 1, then i take appropriate action which corresponds to that bit.

    and select_signal must be controlled by top level GENERIC feature.

    and the generate statement inside main body of module must instantiate appropriate structure with this functionality.
    RADNOR, Jul 20, 2011
    #3
  4. RADNOR

    RADNOR

    Joined:
    Jul 20, 2011
    Messages:
    4
    Ok here is my solution. It generates N amount of muxes, and each mux has N inputs. Each input and output is 16 bits, so total width of output from all muxes is N * 16 bits.
    Code:
    array: for index in N-1 downto 0 generate
    begin
    
    single_mux: process(select_signal) -- generating single mux
    begin
        for j in N-1 downto 0 loop -- and generating its length
            if select_signal(j) = '1' then
            mux_out(j*16+15 downto j*16) <= ...; -- one data
            else
            mux_out(j*16+15 downto j*16) <= ...; -- another data
            end if;
    
        end loop;
    end process;
    
    end generate;
    i think its pretty much something like idea you described.

    But actually i do not thing there will be a penalty, because they all are parallel structures.
    RADNOR, Jul 20, 2011
    #4
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