N e one willing to help with :No feasible entries for infix operation "*"

Discussion in 'VHDL' started by Unity, Jul 24, 2008.

  1. Unity

    Unity

    Joined:
    Apr 6, 2007
    Messages:
    4
    I have the following code and been having trouble with a couple of lines which seem to be causing lots of errors.

    No feasible entries for infix operator "*".

    Original Code................................................................................

    LIBRARY IEEE;
    LIBRARY WORK;
    USE IEEE.NUMERIC_STD.ALL;
    USE WORK.NUMERIC_UNSIGNED.ALL;
    USE IEEE.STD_LOGIC_1164.ALL;

    ENTITY Bit_Destuff IS PORT (
    Clk : IN STD_LOGIC;
    G_Rst : IN STD_LOGIC;
    Arbtr_Sts : IN STD_LOGIC;
    Bit_Destf_Intl : IN STD_LOGIC;
    Sampled_Bit : IN STD_LOGIC;
    Tx_Success : IN STD_LOGIC;
    Rx_Success : IN STD_LOGIC;
    Act_Err_Frm_Tx : IN STD_LOGIC;
    Psv_Err_Frm_Tx : IN STD_LOGIC;
    Ovld_Frm_Tx : IN STD_LOGIC;
    Serial_In : OUT STD_LOGIC;
    Rx_Crc_Frm : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
    Rcvd_Bt_Cnt : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    De_Stuff : OUT STD_LOGIC;
    One_Count : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    Zero_Count : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    Rcvd_Eof_Flg : OUT STD_LOGIC;
    Rcvd_Msg_ID : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
    Rcvd_Rtr : OUT STD_LOGIC;
    Rcvd_Dlc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    Rcvd_Crc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    Rx_Crc_Intl : OUT STD_LOGIC;
    Rx_Crc_Enable : OUT STD_LOGIC;
    Rcvd_Data_Len : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    Rcvd_Data_Frm : OUT STD_LOGIC_VECTOR(63 DOWNTO );
    Rcvd_Lst_Bit_Ifs : OUT STD_LOGIC;
    Rcvd_Crc_Flg : OUT STD_LOGIC;
    Rcvd_Lst_Bit_EOF : OUT STD_LOGIC);
    END ENTITY Bit_Destuff;

    ------------------------------------------------------------------
    SIGNAL Destf_Out : UNSIGNED (63 DOWNTO 0);
    SIGNAL Rcvd_Data_Frm_Pad : UNSIGNED (6 DOWNTO 0);
    SIGNAL Rcvd_Frm_Len : UNSIGNED(6 DOWNTO 0);
    SIGNAL Rcvd_Data_Len_Xhdl7 : UNSIGNED (6 DOWNTO 0);
    ----------------------------------------------------------------------
    Destf_Out_3 <= ("0001000" * Destf_Out(3));
    ----------------------------------------------------------------------
    -- BLOCK TO CALCULATE THE RECEIVED FRAME LENGTH AND RECEIVED DATA LENGTH

    PROCESS (Clk, G_Rst)
    BEGIN
    IF (G_Rst = '1') THEN
    Rcvd_Frm_Len <= "0000000";
    Rcvd_Data_Len_Int <= "0000000";
    Rcvd_Data_Frm_Pad <= "1000000";

    ELSIF (Clk'EVENT AND Clk = '1') THEN
    IF ((Rx_Success OR Tx_Success) = '1') THEN
    Rcvd_Frm_Len <= "0000000";
    Rcvd_Data_Len_Int <= "0000000";
    Rcvd_Data_Frm_Pad<= "1000000";
    ELSE
    IF (Rcvd_Rtr_Int10 = '1') THEN
    Rcvd_Data_Len_Int7 <= "0000000";
    Rcvd_Data_Frm_Pad <= "1000000";
    Rcvd_Frm_Len <= "0100010";
    ELSE
    IF ((Rcvd_Rtr_Int10 = '0') AND (Rcvd_Bt_Cnt_Int2 = "0010101")) THEN
    Rcvd_Data_Len_Int7 <= "0001000" * ("0001000" * Destf_Out(3) + "0000100" * Destf_Out(2) + "0000010" * Destf_Out(1) + "0000001" * Destf_Out(0));
    Rcvd_Data_Frm_Pad <= "1000000" - ("0001000" * ("0001000" * Destf_Out(3) + "0000100" * Destf_Out(2) + "0000010" * Destf_Out(1) + "0000001" * Destf_Out(0)));
    Rcvd_Frm_Len <= "0010011" + ("0001000" * ("0001000" * Destf_Out (3) + "0000100" * Destf_Out (2) + "0000010" * Destf_Out(1) + "0000001" * Destf_Out(0))) + "0001111";
    ELSE
    Rcvd_Frm_Len <= Rcvd_Frm_Len;
    END IF;
    END IF;
    END IF;
    END IF;
    END PROCESS;



    Sorry!!! The code is very long!!! This is just a small part of it. Any help will be appreciated.

    I have another example in the reply thread below. It has the same problem eventhough it uses the Unsigned Function to do the conversion first before multiplying.
     
    Last edited: Jul 25, 2008
    Unity, Jul 24, 2008
    #1
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  2. Unity

    guarana5

    Joined:
    Jul 25, 2008
    Messages:
    3
    you'll have to cast the values. you can't multiply bit-vectors.
     
    guarana5, Jul 25, 2008
    #2
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  3. Unity

    Unity

    Joined:
    Apr 6, 2007
    Messages:
    4
    guarana5,

    Thanks for the reply. Here is another simpler example which should be straight forward. In this example I tried using the multipication function with first converting them to unsigned and then multiplying them. It should work but once again it doesn't. I'm going crazy:hmm2:

    library ieee;
    use ieee.numeric_std.all;
    use ieee.std_logic_1164.all;

    entity testmultun is
    port (
    q : out std_logic_vector(63 downto 0);
    d1 : in std_logic_vector(31 downto 0);
    d2 : in std_logic_vector(15 downto 0));
    end entity testmultun;

    architecture rtl of testmultun is
    signal d1_32un : unsigned(31 downto 0);
    signal d2_16un : unsigned(15 downto 0);
    Signal d3_test : unsigned (15 downto 0);
    signal mult_63un : unsigned(47 downto 0);
    begin -- architecture rtl
    d1_32un <= unsigned(d1);
    d2_16un <= unsigned(d2);
    d3_test <= unsigned (d1(3)* d2); -------->>> Error: No feasible entries for infix operator "*"

    mult_63un <= d1_32un * d2_16un * d3_test;
    q <= std_logic_vector(mult_63un);

    end architecture rtl;
     
    Unity, Jul 25, 2008
    #3
  4. Unity

    guarana5

    Joined:
    Jul 25, 2008
    Messages:
    3
    hej unity!
    in this line you are multiplying std_logic_vectors and trying to cast the result of the multiplication to unsigned - that doesn't work! you have to cast the operands, not the result, as you did here:
    but be careful in regard to size of operands and target!
     
    guarana5, Jul 28, 2008
    #4
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