Natural Arrays inside Records

[mach7]

I'm new to VHDL, so I might not get all the terminology correct, but I want to create a record that contains unconstrained arrays. In particular, I want to do something like

type complex is record (natural range <A>)
    re, im : signed (<A>);
end record;

but of course this is invalid syntax. What I'm trying to avoid is having to create multiple types, e.g.

type complex8 is record
    re, im : signed (7 downto 0);
end record;

type complex16 is record
    re, im : signed (15 downto 0);
end record;

Instead, I want to be able to say

signal x1, x2 : complex(7 downto 0);
signal x3, x4 : complex(15 downto 0);

Any ideas?

Thanks,
-J