NC Verilog and specify block query

A

Anshul Bansal

Hello all


I am trying to use the following specify block in my program.


reg nX1, nX0, X1, X0;


specify


specparam D1=10;
specparam D2=20;
(A0,A1,B0,B1,Xe,en *> nX1) = D1;
(A0,A1,B0,B1,Xe,en *> nX0) = D1;
(A0,A1,B0,B1,Xe,en *> X0) = D2;
(A0,A1,B0,B1,Xe,en *> X1) = D2;


endspecify


When I try to compile this entire design in NC Verilog simulator then
it gives me an error that
"Register Encountered in specify block".


does this mean I can't use registers in specify block.


Moreover when I compile the same design in Modelsim simulator, it
compiles properly without giving any error.


Please help asap.


thanks


anshul
 
P

Paul Uiterlinden

Anshul said:
Hello all


I am trying to use the following specify block in my program.

Why are you posting a Verilog question in a VHDL newsgroup?
It's not that you don't know the existance of c.l.verilog: you've posted
exact the same question in that newsgroup.

Paul.
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,483
Members
44,901
Latest member
Noble71S45

Latest Threads

Top