NC Verilog and specify block query

Discussion in 'VHDL' started by Anshul Bansal, Mar 14, 2005.

  1. Hello all


    I am trying to use the following specify block in my program.


    reg nX1, nX0, X1, X0;


    specify


    specparam D1=10;
    specparam D2=20;
    (A0,A1,B0,B1,Xe,en *> nX1) = D1;
    (A0,A1,B0,B1,Xe,en *> nX0) = D1;
    (A0,A1,B0,B1,Xe,en *> X0) = D2;
    (A0,A1,B0,B1,Xe,en *> X1) = D2;


    endspecify


    When I try to compile this entire design in NC Verilog simulator then
    it gives me an error that
    "Register Encountered in specify block".


    does this mean I can't use registers in specify block.


    Moreover when I compile the same design in Modelsim simulator, it
    compiles properly without giving any error.


    Please help asap.


    thanks


    anshul
    Anshul Bansal, Mar 14, 2005
    #1
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  2. Anshul Bansal wrote:
    > Hello all
    >
    >
    > I am trying to use the following specify block in my program.


    Why are you posting a Verilog question in a VHDL newsgroup?
    It's not that you don't know the existance of c.l.verilog: you've posted
    exact the same question in that newsgroup.

    Paul.
    Paul Uiterlinden, Mar 14, 2005
    #2
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