ncelab // synplify_pro // qu(at)rtus //

Discussion in 'VHDL' started by bossbebes, Jul 8, 2008.

  1. bossbebes

    bossbebes

    Joined:
    Jul 8, 2008
    Messages:
    1
    Hi everybody

    I m designing digital electronic entity to be place in an stratixii fpga.
    I m using synplify pro to compile my RTL level design, output file .vqm
    Then I generate a vhdl netlist with the qu(at)rtus software + timing (sdo + vho) in order to simulate this netlist with simvision.
    And when I try to elaborate my testbench (which include my top level design netlist) with the ncelab command from cadence, I got thoses errors (all similar to this one):

    ncelab: *W,SDFVHSSV: VHDL port corresponding to scalar SDF port 'dataa' is a vector &lt./simulation/ncsim/nce_test_pattern_card_top_vhd.sdo, line 279397>.

    And if i go to the mentionned line in the sdo file :
    (CELL
    (CELLTYPE 'stratixii_lcell_ff')
    (INSTANCE \\pio_mux\|sel_22\[2\]\~DUPLICATE\\)
    (DELAY
    (ABSOLUTE
    (PORT clk (2501:2501:2501) (2591:2591:2591))
    (PORT adatasdata (3129:3129:3129) (3643:3643:3643))
    (PORT aclr (2217:2217:2217) (2308:2308:2308))
    (PORT ena (1781:1781:1781) (1875:1875:1875))
    (IOPATH (posedge clk) regout (109:109:109) (109:109:109))
    (IOPATH (posedge aclr) regout (245:245:245) (245:245:245))
    )
    ) <<<<<&lt----------XXXXXXXXX here is the mentionned line
    (TIMINGCHECK
    (SETUP adatasdata (posedge clk) (104:104:104))
    (SETUP ena (posedge clk) (104:104:104))
    (HOLD adatasdata (posedge clk) (172:172:172))
    (HOLD ena (posedge clk) (172:172:172))
    )
    )

    I confused about that, look like the error do not match with sdo file.

    I got an answer from @ltera support :
    '
    I have seen similar errors to this before, the error is stating that you have a port type miss match in your design, either data width or data type.

    The normal cause of this error is a std_logic port connected to a std_logic_vector (0 downto 0). Some VHDL tools will allow these connections but other will not.

    I would recommend checking the top level ports of your design in the .vho for port widths and data types (the .vho is just standard vhdl).

    I would also recommend checking you have compiled the @ltera VHDL libraries from the correct version of qu(at)rtus II.
    '

    Actually I had some std_logic connected to std_ulogic_vector(0 downto 0).
    But not on top level port, on signal and ff_cells.
    I removed all the std_logic_vector(0 downto 0) and changed then by std_logic.

    And I still have same problems :
    ncelab: *W,SDFVHSSV: VHDL port corresponding to scalar SDF port 'd' is a vector &lt./simulation/ncsim/nce_test_pattern_card_top_vhd.sdo, line 545469>.

    What can I do ?

    Does anybody had been confronted to this problem

    Thanks a lot for your help.

    Regards

    Vincent, a bit lost
    bossbebes, Jul 8, 2008
    #1
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