M
Metin Yerlikaya
Hi,
i have the following problem & appreciate any hints on this.
i used ncverilog all the time before. There, it was possible to use
system tasks($recordvar) within the testbench to write out *trn & *dsn
files which you one can use later with signalscan for debugging signal
waveforms.
Now i have to use vhdl and ncvhdl. Is it true that above method is not
possible for vhdl testbenchs.
How can i generate *trn *dsn. files with vhdl. Whats the most straight
and sophisticated way to do this. I don't want to use nclaunch nor
interactive ncsim tcl shell. I want to run the ncsim and later if
needed check the waveforms.
Another question:
would it work if i write a verilog testbench and instantiate vhdl top
level and use verilog system tasks to generate waveform files? What
are the command line then to compile&elab and invoke the
simulator(ncsim) ?
many thanks!!
Metin
i have the following problem & appreciate any hints on this.
i used ncverilog all the time before. There, it was possible to use
system tasks($recordvar) within the testbench to write out *trn & *dsn
files which you one can use later with signalscan for debugging signal
waveforms.
Now i have to use vhdl and ncvhdl. Is it true that above method is not
possible for vhdl testbenchs.
How can i generate *trn *dsn. files with vhdl. Whats the most straight
and sophisticated way to do this. I don't want to use nclaunch nor
interactive ncsim tcl shell. I want to run the ncsim and later if
needed check the waveforms.
Another question:
would it work if i write a verilog testbench and instantiate vhdl top
level and use verilog system tasks to generate waveform files? What
are the command line then to compile&elab and invoke the
simulator(ncsim) ?
many thanks!!
Metin