ncvhdl problem

Discussion in 'VHDL' started by Metin Yerlikaya, Jan 22, 2005.

  1. Hi,

    i have the following problem & appreciate any hints on this.

    i used ncverilog all the time before. There, it was possible to use
    system tasks($recordvar) within the testbench to write out *trn & *dsn
    files which you one can use later with signalscan for debugging signal
    waveforms.

    Now i have to use vhdl and ncvhdl. Is it true that above method is not
    possible for vhdl testbenchs.
    How can i generate *trn *dsn. files with vhdl. Whats the most straight
    and sophisticated way to do this. I don't want to use nclaunch nor
    interactive ncsim tcl shell. I want to run the ncsim and later if
    needed check the waveforms.

    Another question:

    would it work if i write a verilog testbench and instantiate vhdl top
    level and use verilog system tasks to generate waveform files? What
    are the command line then to compile&elab and invoke the
    simulator(ncsim) ?


    many thanks!!
    Metin
    Metin Yerlikaya, Jan 22, 2005
    #1
    1. Advertising

  2. Metin Yerlikaya

    Ajeetha Guest

    Hi,
    Use TCL in batch mode, you don't need to do it interactively, try the
    following tcl file:

    -- tcl file

    database -open waves -shm -default
    probe -shm -all -depth all top
    run
    exit
    ----

    Use it with ncsim -input dump.tcl <other options>

    HTH,
    Ajeetha
    http://www.noveldv.com
    Metin Yerlikaya wrote:
    > Hi,
    >
    > i have the following problem & appreciate any hints on this.
    >
    > i used ncverilog all the time before. There, it was possible to use
    > system tasks($recordvar) within the testbench to write out *trn &

    *dsn
    > files which you one can use later with signalscan for debugging

    signal
    > waveforms.
    >
    > Now i have to use vhdl and ncvhdl. Is it true that above method is

    not
    > possible for vhdl testbenchs.
    > How can i generate *trn *dsn. files with vhdl. Whats the most

    straight
    > and sophisticated way to do this. I don't want to use nclaunch nor
    > interactive ncsim tcl shell. I want to run the ncsim and later if
    > needed check the waveforms.
    >
    > Another question:
    >
    > would it work if i write a verilog testbench and instantiate vhdl top
    > level and use verilog system tasks to generate waveform files? What
    > are the command line then to compile&elab and invoke the
    > simulator(ncsim) ?
    >
    >
    > many thanks!!
    > Metin
    Ajeetha, Jan 22, 2005
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Anand P Paralkar

    NCVHDL/NCELAB and Recursive Instantiation

    Anand P Paralkar, Nov 10, 2003, in forum: VHDL
    Replies:
    2
    Views:
    3,051
    Mike Treseler
    Nov 10, 2003
  2. Lily

    cadence NCVHDL simulation

    Lily, Apr 27, 2004, in forum: VHDL
    Replies:
    4
    Views:
    1,957
  3. kish

    ncvhdl error

    kish, May 20, 2004, in forum: VHDL
    Replies:
    2
    Views:
    745
  4. Replies:
    0
    Views:
    1,517
  5. Jim
    Replies:
    2
    Views:
    1,276
Loading...

Share This Page