near "PROCEDURE": expecting: END

Discussion in 'VHDL' started by swapsap1, Aug 13, 2007.

  1. swapsap1

    swapsap1

    Joined:
    Aug 13, 2007
    Messages:
    1
    Modelsim 6.1b;wHY SHOULD i GET THIS ERROR AT COLORED LINE::----

    ** Error: testbench.vhdl(69): near "PROCEDURE": expecting: END
    ** Error: testbench.vhdl(82): near "procedure": syntax error
    //////////////////////////////////////////////////////////////////////////

    ------------------------------------------------------------------------------
    use std.textio.all;
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.numeric_std.ALL;
    use ieee.std_logic_textio.all ;




    ENTITY ram_tb IS
    END ram_tb;

    ARCHITECTURE testbench OF ram_tb IS

    COMPONENT seamem1
    PORT (
    SeaRamWZ_0 : in STD_LOGIC;
    SeaRamEZ_0 : in STD_LOGIC;
    SeaRamClk_0 : in STD_LOGIC;
    SeaRamWrenz_0 : in STD_LOGIC_VECTOR(31 downto 0);
    SeaRamA_0 : in STD_LOGIC_VECTOR(10 downto 0);
    SeaRamWD_0 : in STD_LOGIC_VECTOR(31 downto 0);
    SeaRamRD_0 : out STD_LOGIC_VECTOR(31 downto 0)
    );
    END COMPONENT;


    CONSTANT clk_pd : time := 100 ns;

    -------------------------------------------
    -- Intermediate signals specfic to Single Port DUT pins
    -------------------------------------------


    --SIGNAL s_SeaRamWZ_0 : std_logic:='0';
    --SIGNAL s_SeaRamWZ_0 : std_logic:='0';
    SIGNAL s_SeaRamWZ_0 : std_logic;
    SIGNAL s_SeaRamEZ_0 : std_logic;

    SIGNAL s_SeaRamClk_0 : std_logic;
    SIGNAL s_SeaRamWrenz_0 : std_logic_vector(31 DOWNTO 0);
    SIGNAL s_SeaRamA_0 : std_logic_vector(10 DOWNTO 0);
    SIGNAL s_SeaRamWD_0 : std_logic_vector(31 DOWNTO 0);
    SIGNAL s_SeaRamRD_0 : std_logic_vector(31 DOWNTO 0);
    ---------------------------------------------------
    -- instantiations of single-port RAM architectures.
    -- All architectures behave equivalently, but they
    -- have different implementations. The signal-based
    -- architecture (rtl) is not a recommended style.
    ---------------------------------------------------


    begin



    spram1: seamem1
    PORT MAP(s_SeaRamWZ_0,s_SeaRamEZ_0,s_SeaRamClk_0,s_SeaRamWrenz_0,s_SeaRamA_0,s_SeaRamWD_0,s_SeaRamRD_0 );


    PROCEDURE sp_write ( constant address : std_logic_vector (10 downto 0);
    constant data : std_logic_vector (31 downto 0);
    constant bit_enable: std_logic_vector (31 downto 0)
    ) is


    begin -- sp_write

    s_SeaRamWZ_0 <='0';
    s_SeaRamWrenz_0 <=bit_enable;
    s_SeaRamA_0 <= address ;
    s_SeaRamWD_0 <= data ;
    END sp_write;

    procedure sp_read (constant address : std_logic_vector (10 downto 0);
    constant data_expected : std_logic_vector (31 downto 0)
    ) is

    begin -- sp_read

    s_SeaRamWZ_0 <='1';
    s_SeaRamA_0 <= address ;


    assert (s_SeaRamWD_0 /=data_expected)
    report " invalid read value"
    severity Error;
    end sp_read;





    -------------------------------------------
    -- clock generator
    -------------------------------------------
    clock_driver : PROCESS
    BEGIN
    s_SeaRamClk_0 <= '0';
    WAIT FOR clk_pd / 2;
    LOOP
    s_SeaRamClk_0 <= '1', '0' AFTER clk_pd / 2;
    WAIT FOR clk_pd;
    END LOOP;
    END PROCESS;

    -------------------------------------------
    -- simulation control process
    -------------------------------------------
    ctrl_sim : PROCESS
    BEGIN


    FOR i IN 0 TO 1023 LOOP

    s_SeaRamEZ_0 <= '0';

    --Write Operation
    --s_SeaRamWZ_0 <='0';

    --s_SeaRamWD_0 <= conv_std_logic_vector(1000 + i, s_SeaRamWD_0'length);
    --s_SeaRamA_0 <= conv_std_logic_vector(4*i, s_SeaRamA_0'length);
    --sp_write(address,data,bit_enable,mode);
    sp_write(conv_std_logic_vector(4*i, s_SeaRamA_0'length),conv_std_logic_vector(1000 + i, s_SeaRamWD_0'length),(others => '0'));
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';

    --s_SeaRamWD_0 <= conv_std_logic_vector(2000 + i, s_SeaRamWD_0'length);
    --s_SeaRamA_0 <= conv_std_logic_vector(8*i, s_SeaRamA_0'length);

    sp_write(conv_std_logic_vector(8*i, s_SeaRamA_0'length),conv_std_logic_vector(2000 + i, s_SeaRamWD_0'length),(others => '0'));

    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';

    --s_SeaRamWD_0 <= conv_std_logic_vector(3000, s_SeaRamWD_0'length);
    --s_SeaRamA_0 <= conv_std_logic_vector(16, s_SeaRamA_0'length);
    sp_write(conv_std_logic_vector(16, s_SeaRamA_0'length),conv_std_logic_vector(4000, s_SeaRamWD_0'length),(others => '0'));

    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    --Read Operation
    --s_SeaRamWZ_0 <='1';
    --s_SeaRamA_0 <= conv_std_logic_vector(4*i, s_SeaRamA_0'length);

    --sp_read (address,data_expected,mode );

    sp_read (conv_std_logic_vector(4*i, s_SeaRamA_0'length),conv_std_logic_vector(1000 + i, s_SeaRamWD_0'length));

    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    --s_SeaRamA_0 <= conv_std_logic_vector(8*i, s_SeaRamA_0'length);
    sp_read (conv_std_logic_vector(8*i, s_SeaRamA_0'length),conv_std_logic_vector(2000 + i, s_SeaRamWD_0'length));

    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';













    -- s_SeaRamWrenz_0 <= (others => '0');
    -- s_SeaRamEZ_0 <= '0';
    --
    -- --Write Operation
    -- s_SeaRamWZ_0 <='0';

    -- s_SeaRamWD_0 <= conv_std_logic_vector(1000 + i, s_SeaRamWD_0'length);
    -- s_SeaRamA_0 <= conv_std_logic_vector(4*i, s_SeaRamA_0'length);
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';

    -- s_SeaRamWD_0 <= conv_std_logic_vector(2000 + i, s_SeaRamWD_0'length);
    -- s_SeaRamA_0 <= conv_std_logic_vector(8*i, s_SeaRamA_0'length);
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';

    -- s_SeaRamWD_0 <= conv_std_logic_vector(3000, s_SeaRamWD_0'length);
    -- s_SeaRamA_0 <= conv_std_logic_vector(16, s_SeaRamA_0'length);
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- --Read Operation
    -- s_SeaRamWZ_0 <='1';
    -- s_SeaRamA_0 <= conv_std_logic_vector(4*i, s_SeaRamA_0'length);
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- s_SeaRamA_0 <= conv_std_logic_vector(8*i, s_SeaRamA_0'length);
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';
    -- WAIT UNTIL s_SeaRamClk_0'EVENT AND s_SeaRamClk_0 = '0';



    END LOOP;
    ASSERT false
    REPORT "### End of Simulation!"
    SEVERITY failure;
    END PROCESS;




    END testbench;
    swapsap1, Aug 13, 2007
    #1
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